@@ -45,6 +45,7 @@
#define UART4_BASE_ADDR 0x30A60000
#define USDHC1_BASE_ADDR 0x30B40000
#define USDHC2_BASE_ADDR 0x30B50000
+#define QSPI0_AMBA_BASE 0x08000000
#ifdef CONFIG_IMX8MM
#define USDHC3_BASE_ADDR 0x30B60000
#endif
@@ -13,8 +13,18 @@
#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define UBOOT_ITB_OFFSET 0x57C00
+#define FSPI_CONF_BLOCK_SIZE 0x1000
+#define UBOOT_ITB_OFFSET_FSPI \
+ (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
+
+#ifdef CONFIG_FSPI_CONF_HEADER
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
+#else
#define CONFIG_SYS_UBOOT_BASE \
- (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#endif
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x920000