From patchwork Sun Oct 28 12:30:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 989974 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42jcZz3gJ6z9sDN for ; Sun, 28 Oct 2018 23:33:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 36426C21C6A; Sun, 28 Oct 2018 12:33:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 565E4C21D4A; Sun, 28 Oct 2018 12:32:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E299AC21C29; Sun, 28 Oct 2018 12:32:42 +0000 (UTC) Received: from mx.tkos.co.il (guitar.tcltek.co.il [192.115.133.116]) by lists.denx.de (Postfix) with ESMTPS id 9377FC21C29 for ; Sun, 28 Oct 2018 12:32:41 +0000 (UTC) Received: from tarshish.tkos.co.il (unknown [10.0.8.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id CD31A44085F; Sun, 28 Oct 2018 14:32:39 +0200 (IST) From: Baruch Siach To: u-boot@lists.denx.de, Prafulla Wadaskar , Luka Perkov , Stefan Roese Date: Sun, 28 Oct 2018 14:30:55 +0200 Message-Id: <6b10010c0f58600be7ed86ef8ae2691e023bab99.1540729855.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.19.1 In-Reply-To: <56ec45e62aa192e32e5a151f4b2a9a092909b1de.1540729855.git.baruch@tkos.co.il> References: <56ec45e62aa192e32e5a151f4b2a9a092909b1de.1540729855.git.baruch@tkos.co.il> MIME-Version: 1.0 Cc: Grzegorz Jaszczyk , Baruch Siach , Ori Shemtov , Rabeeh Khoury Subject: [U-Boot] [PATCH 2/2] arm64: mvebu: a8k: autodetect RAM size X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from external DIMM. Hard coding the RAM size in the device-tree is not convenient. Fortunately, the ATF that initializes the RAM knows the size of RAM, and U-Boot can query the ATF using a SMC call. This code in this commit is mostly taken from downstream Marvell U-Boot code by Grzegorz Jaszczyk. CONFIG_NR_DRAM_BANKS must be set to 2 to use more than 3GB RAM. Cc: Grzegorz Jaszczyk Signed-off-by: Baruch Siach --- arch/arm/mach-mvebu/arm64-common.c | 47 +++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index f47273fde9c6..7ba7301c7a8c 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -45,15 +46,59 @@ const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) /* DRAM init code ... */ +#define MV_SIP_DRAM_SIZE 0x82000010 + +static u64 a8k_dram_scan_ap_sz(void) +{ + struct pt_regs pregs; + + pregs.regs[0] = MV_SIP_DRAM_SIZE; + pregs.regs[1] = SOC_REGS_PHY_BASE; + smc_call(&pregs); + + return pregs.regs[0]; +} + +static void a8k_dram_init_banksize(void) +{ + /* + * Config 2 DRAM banks: + * Bank 0 - max size 4G - 1G + * Bank 1 - ram size - 4G + 1G + */ + phys_size_t max_bank0_size = SZ_4G - SZ_1G; + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size <= max_bank0_size) { + gd->bd->bi_dram[0].size = gd->ram_size; + return; + } + + gd->bd->bi_dram[0].size = max_bank0_size; + if (CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = SZ_4G; + gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + } +} + int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + if (CONFIG_IS_ENABLED(ARMADA_8K)) + a8k_dram_init_banksize(); + else + fdtdec_setup_memory_banksize(); return 0; } int dram_init(void) { + if (CONFIG_IS_ENABLED(ARMADA_8K)) { + gd->ram_size = a8k_dram_scan_ap_sz(); + if (gd->ram_size != 0) + return 0; + } + if (fdtdec_setup_mem_size_base() != 0) return -EINVAL;