From patchwork Mon Apr 13 04:48:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 460632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 93FBE1402F4 for ; Mon, 13 Apr 2015 14:50:29 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 81E7BA7479; Mon, 13 Apr 2015 06:49:51 +0200 (CEST) X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "References" Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V_Lt_BmKIxeA; Mon, 13 Apr 2015 06:49:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BC078A7436; Mon, 13 Apr 2015 06:49:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 11B4AA742D for ; Mon, 13 Apr 2015 06:48:50 +0200 (CEST) X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "References" Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aHp15w_8Kngs for ; Mon, 13 Apr 2015 06:48:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from thoth.sbs.de (thoth.sbs.de [192.35.17.2]) by theia.denx.de (Postfix) with ESMTPS id 1AD244A03B for ; Mon, 13 Apr 2015 06:48:47 +0200 (CEST) Received: from mail1.siemens.de (localhost [127.0.0.1]) by thoth.sbs.de (8.14.3/8.14.3) with ESMTP id t3D4mUcL009074; Mon, 13 Apr 2015 06:48:30 +0200 Received: from md1f2u6c.ww002.siemens.net (md1czxqc.ww300.siemens.net [139.22.39.75]) by mail1.siemens.de (8.14.3/8.14.3) with SMTP id t3D4mMCb024251; Mon, 13 Apr 2015 06:48:30 +0200 From: Jan Kiszka To: U-Boot Mailing List , Tom Rini Date: Mon, 13 Apr 2015 06:48:19 +0200 Message-Id: <5efdd2dfb278a38919aaf8185183052460a762ea.1428900500.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: In-Reply-To: References: Cc: Tom Warren , Paul Walmsley , Ian Campbell , Thierry Reding Subject: [U-Boot] [PATCH v6 14/15] ARM: tegra: Enable SMMU when going non-secure X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits. Signed-off-by: Thierry Reding Signed-off-by: Jan Kiszka --- arch/arm/include/asm/arch-tegra124/mc.h | 2 ++ arch/arm/mach-tegra/ap.c | 40 +++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index 5557732..37998a4 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -74,6 +74,8 @@ struct mc_ctlr { u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ }; +#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) + #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 869a2ed..0b94e8a 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -169,6 +169,43 @@ void protect_secure_section(void) } #endif +#if defined(CONFIG_ARMV7_NONSEC) +static void smmu_flush(struct mc_ctlr *mc) +{ + (void)readl(&mc->mc_smmu_config); +} + +static void smmu_enable(void) +{ + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; + u32 value; + + /* + * Enable translation for all clients since access to this register + * is restricted to TrustZone-secured requestors. The kernel will use + * the per-SWGROUP enable bits to enable or disable translations. + */ + writel(0xffffffff, &mc->mc_smmu_translation_enable_0); + writel(0xffffffff, &mc->mc_smmu_translation_enable_1); + writel(0xffffffff, &mc->mc_smmu_translation_enable_2); + writel(0xffffffff, &mc->mc_smmu_translation_enable_3); + + /* + * Enable SMMU globally since access to this register is restricted + * to TrustZone-secured requestors. + */ + value = readl(&mc->mc_smmu_config); + value |= TEGRA_MC_SMMU_CONFIG_ENABLE; + writel(value, &mc->mc_smmu_config); + + smmu_flush(mc); +} +#else +static void smmu_enable(void) +{ +} +#endif + void s_init(void) { /* Init PMC scratch memory */ @@ -179,6 +216,9 @@ void s_init(void) /* init the cache */ config_cache(); + /* enable SMMU */ + smmu_enable(); + /* init vpr */ config_vpr(); }