From patchwork Mon Mar 21 11:18:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 600072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qTCxr3zRnz9s5l for ; Mon, 21 Mar 2016 22:18:39 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B18F8A7516; Mon, 21 Mar 2016 12:18:35 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id S1PCqw79ot_m; Mon, 21 Mar 2016 12:18:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9DFA3A7498; Mon, 21 Mar 2016 12:18:34 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 813C5A748F for ; Mon, 21 Mar 2016 12:18:30 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6FjyhUzy_f2s for ; Mon, 21 Mar 2016 12:18:30 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.9]) by theia.denx.de (Postfix) with ESMTPS id 429E7A745C for ; Mon, 21 Mar 2016 12:18:26 +0100 (CET) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3qTCxZ14hBz3hjGj; Mon, 21 Mar 2016 12:18:26 +0100 (CET) X-Auth-Info: bebwwkCDJt7GpEBd0ExkzCQyP15LwxXnSFWg3cAc04E= Received: from [IPv6:::1] (unknown [195.140.253.167]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by smtp-auth.mnet-online.de (Postfix) with ESMTPSA id 3qTCxY4cdMzvdWV; Mon, 21 Mar 2016 12:18:24 +0100 (CET) Message-ID: <56EFD87A.90208@denx.de> Date: Mon, 21 Mar 2016 12:18:18 +0100 From: Marek Vasut User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 MIME-Version: 1.0 To: "Bakhvalov, Denis (Nokia - PL/Wroclaw)" , Dinh Nguyen References: <56D97FE1.4090108@gmail.com> <56DAD2DC.2070000@gmail.com> <56E02974.4060801@gmail.com> <56E0983D.6090304@opensource.altera.com> <56E0BEF0.5070906@denx.de> <56E16BF9.1080108@denx.de> In-Reply-To: Cc: "u-boot@lists.denx.de" , Chin Liang See Subject: Re: [U-Boot] Ethernet not found on Arria 5. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On 03/21/2016 09:16 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote: > Hi, Hi! > I solved the Ethernet problem on our board. > > The problem was in the register below: > > Link: http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html > Registers used by the EMACs. All fields are reset by a cold or warm reset. > Module Instance Base Address Register Address > sysmgr 0xFFD08000 0xFFD08060 Thanks for looking into it, try if the attached patch works for you. Make sure you have correct phy-mode = "gmii"; DT node specified for the GMAC you use, Arria V SoCDK surely uses phy-mode = "rgmii"; > I found that difference while comparing the dumps between OK and NOK cases. > > In new U-Boot (2016) the values of > ctrl :: physel_0 > ctrl :: physel_1 > were always set to > 0x1 Select RGMII PHY interface > > I changed this value to > 0x0 Select GMII/MII PHY interface [...] > But still I have this sort of question: > Why those two registers are always assigned to RGMII PHY interface (and default value is 0x2 Select RMII PHY interface)? > In current code there is no way to change this value. Most likely because noone ever had a board with PHY connected over anything else but RGMII, so this went unnoticed. > I changed it like this: > > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c > old mode 100644 > new mode 100755 > index 9b43b92..295ed5a > --- a/arch/arm/mach-socfpga/misc.c > +++ b/arch/arm/mach-socfpga/misc.c > @@ -23,6 +23,8 @@ > > @@ -97,14 +99,19 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) > SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); > > /* configure to PHY interface select choosed */ > +#ifdef CONFIG_WORKAROUND > + setbits_le32(&sysmgr_regs->emacgrp_ctrl, > + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII << physhift); > +#else > setbits_le32(&sysmgr_regs->emacgrp_ctrl, > SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); > +#endif > > /* Release the EMAC controller from reset */ > socfpga_per_reset(reset, 0); > } > > Please evaluate my correction. > Maybe we can assign ctrl :: physel_0 and ctrl :: physel_1 based on some switch in config? We should parse the OF node phy-mode, which describes which mode your PHY uses. If your DT is written correctly, then with the attached patch, any PHY mode should work. > Best regards, > Denis Bakhvalov > From 7dff237a37fe9585613c5bdab597b18bc3e1daa5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Mar 2016 12:06:47 +0100 Subject: [PATCH] arm: socfpga: Handle phy-mode OF property for GMACs Thus far, the socfpga init code had hard-coded the configuration of the ethernet PHY interface to RGMII in the ethernet registers in sysmgr space, so PHYs connected in another modes did not work. This patch fixes support for configurations where the ethernet PHYs are connected over MII/GMII/RMII interfaces by parsing the phy-mode OF property of the GMACs and configuring the ethernet registers in sysmgr space accordingly. Signed-off-by: Marek Vasut Reported-by: Denis Bakhvalov Cc: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ce3ff0a..5f988e3 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -77,7 +77,8 @@ void v7_outer_cache_disable(void) * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id) +static void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) { u32 physhift, reset; @@ -98,16 +99,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) /* configure to PHY interface select choosed */ setbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + phymode << physhift); /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); } +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + static int socfpga_eth_reset(void) { const void *fdt = gd->fdt_blob; struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; int nodes[2]; /* Max. two GMACs */ int ret, count; int i, node; @@ -132,7 +158,14 @@ static int socfpga_eth_reset(void) continue; } - dwmac_deassert_reset(args.args[0]); + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); } return 0; -- 2.7.0