From patchwork Thu Dec 17 17:30:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Purna Chandra Mandal X-Patchwork-Id: 558469 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 49BAC140187 for ; Fri, 18 Dec 2015 04:32:08 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF51B4BC93; Thu, 17 Dec 2015 18:32:06 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HM0xz5pRtuUY; Thu, 17 Dec 2015 18:32:06 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61D974BC72; Thu, 17 Dec 2015 18:32:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1A1AC4BC72 for ; Thu, 17 Dec 2015 18:32:03 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OAa1t-8lds1N for ; Thu, 17 Dec 2015 18:32:03 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from email.microchip.com (exsmtp01.microchip.com [198.175.253.37]) by theia.denx.de (Postfix) with ESMTPS id 435764BC71 for ; Thu, 17 Dec 2015 18:32:02 +0100 (CET) Received: from [10.41.20.11] (10.10.76.4) by CHN-SV-EXCH01.mchp-main.com (10.10.76.37) with Microsoft SMTP Server id 14.3.181.6; Thu, 17 Dec 2015 10:32:00 -0700 To: From: Purna Chandra Mandal Message-ID: <5672F125.50705@microchip.com> Date: Thu, 17 Dec 2015 23:00:13 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 Cc: Cristian Birsan - M91496 Subject: [U-Boot] [PATCH v1 06/18] MIPS: Add support for Microchip PIC32MZ[DA] SoC family. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Purna Chandra Mandal --- arch/mips/dts/pic32mzda.dtsi | 59 +++++++++++++++ arch/mips/include/asm/arch-pic32/pic32.h | 3 + arch/mips/mach-pic32/Kconfig | 16 +++- arch/mips/mach-pic32/Makefile | 2 +- arch/mips/mach-pic32/cpu.c | 121 ++++++++++++++++++++++++++++++- arch/mips/mach-pic32/lowlevel_init.S | 41 +++++++++++ arch/mips/mach-pic32/reset.c | 22 ++++++ 7 files changed, 261 insertions(+), 3 deletions(-) create mode 100644 arch/mips/dts/pic32mzda.dtsi create mode 100644 arch/mips/mach-pic32/lowlevel_init.S create mode 100644 arch/mips/mach-pic32/reset.c diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi new file mode 100644 index 0000000..1333573 --- /dev/null +++ b/arch/mips/dts/pic32mzda.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright 2015 Microchip Technology, Inc. + * Purna Chandra Mandal, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "microchip,pic32mzda", "microchip,pic32mz"; + + cpus { + cpu@0 { + compatible = "mips,mips14kc"; + }; + }; + + clock: clk@1f801200 { + compatible = "microchip,pic32mzda_clk"; + reg = <0xbf801200 0x1000>; + }; + + uart1: serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0xbf822000 0x50>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0xbf822200 0x50>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart6: serial@1f822a00 { + compatible = "microchip,pic32mzda-uart"; + reg = <0xbf822a00 0x50>; + interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + evic: interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xbf810000 0x1000>; + }; + + pinctrl: pinctrl@1f801400 { + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0xbf801400 0x100>, /* in */ + <0xbf801500 0x200>; /* out */ + status = "disabled"; + }; +}; diff --git a/arch/mips/include/asm/arch-pic32/pic32.h b/arch/mips/include/asm/arch-pic32/pic32.h index 4f2084f..d3f428f 100644 --- a/arch/mips/include/asm/arch-pic32/pic32.h +++ b/arch/mips/include/asm/arch-pic32/pic32.h @@ -142,4 +142,7 @@ struct pic32_reg_atomic { u32 inv; }; +/* Core */ +char *get_core_name(void); + #endif /* __PIC32_REGS_H__ */ diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig index e4eaf5c..9983131 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -2,11 +2,23 @@ menu "Microchip PIC32 platforms" depends on MACH_PIC32 config SYS_SOC - default "none" + default "pic32mzda" if SOC_PIC32MZDA choice prompt "PIC32 SoC select" +config SOC_PIC32MZDA + bool "Microchip PIC32MZ[DA] family" + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + select DM_SERIAL + select PIC32_SERIAL + select PIC32_PINCTRL + help + This supports Microchip PIC32MZ[DA] family of microcontrollers. + endchoice choice @@ -16,5 +28,7 @@ endchoice config PIC32_SUPPORTS_FDT_BOOT bool "FDT Boot" + select MIPS_BOOT_FDT + select MIPS_BOOT_CMDLINE_LEGACY endmenu diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile index cb42607..03d5f27 100644 --- a/arch/mips/mach-pic32/Makefile +++ b/arch/mips/mach-pic32/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y = cpu.o +obj-y = cpu.o reset.o lowlevel_init.o \ No newline at end of file diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index 58fd3ab..f95beae 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -6,8 +6,127 @@ * */ #include +#include +#include +#include +#include +#include +#include +#include +#include -phys_size_t initdram(int board_type) +DECLARE_GLOBAL_DATA_PTR; + +static ulong clk_get_cpu_rate(void) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + panic("uclass-clk: device not found\n"); + return 0; + } + + return clk_get_rate(dev); +} + +/* initialize prefetch module related to cpu_clk */ +static void init_prefetch(void) +{ + int v, nr_waits; + ulong rate; + + rate = clk_get_cpu_rate(); + + /* calc and apply waits based on dynamic ECC */ + v = (readl(CFGCON) >> 4) & 0x03; + if (v < 2) { + if (rate < 66000000) + nr_waits = 0; + else if (rate < 133000000) + nr_waits = 1; + else + nr_waits = 2; + } else { + if (rate <= 83000000) + nr_waits = 0; + else if (rate <= 166000000) + nr_waits = 1; + else + nr_waits = 2; + } + + writel(nr_waits, PRECON); + + /* Enable prefetch for all */ + writel(0x30, PRECONSET); +} + +/* arch specific CPU init after DM */ +int arch_cpu_init_dm(void) +{ + /* flash prefetch */ + init_prefetch(); + + return 0; +} + +/* initializes board before relocation */ +__attribute__ ((weak)) int board_early_init_f(void) { return 0; } + +int misc_init_r(void) +{ + set_io_port_base(0); + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +char *get_core_name(void) +{ + u32 proc_id; + char *str; + + proc_id = read_c0_prid(); + switch (proc_id) { + case 0x19e28: + str = "PIC32MZ[DA]"; + break; + default: + str = "UNKNOWN"; + } + + return str; +} +#endif + +#ifdef CONFIG_CMD_CLK +int soc_clk_dump(void) +{ + int i, ret; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + printf("clk-uclass not found\n"); + return ret; + } + + printf("PLL Speed: %lu MHz\n", + clk_get_periph_rate(dev, PLLCLK) / 1000000); + + printf("CPU Clock Speed: %lu MHz\n", clk_get_rate(dev) / 1000000); + + for (i = PB1CLK; i <= PB7CLK; i++) + printf("PB%d Clock Speed: %lu MHz\n", + i - PB1CLK + 1, clk_get_periph_rate(dev, i) / 1000000); + + for (i = REF1CLK; i <= REF5CLK; i++) + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, + clk_get_periph_rate(dev, i) / 1000000); + return 0; +} +#endif diff --git a/arch/mips/mach-pic32/lowlevel_init.S b/arch/mips/mach-pic32/lowlevel_init.S new file mode 100644 index 0000000..9c11761 --- /dev/null +++ b/arch/mips/mach-pic32/lowlevel_init.S @@ -0,0 +1,41 @@ +/* + * (c) 2015 Purna Chandra Mandal + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#include +#include +#include + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + + /* + * Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + /* Initialize 'boot_flags' to zero. */ + li a0, 0x00000000 + + jr ra + nop diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c new file mode 100644 index 0000000..0d1f8fe --- /dev/null +++ b/arch/mips/mach-pic32/reset.c @@ -0,0 +1,22 @@ +/* + * (c) 2015 Purna Chandra Mandal + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include + +void _machine_restart(void) +{ + writel(0, SYSKEY); + writel(0xAA996655, SYSKEY); + writel(0x556699AA, SYSKEY); + writel(0x1, RSWRST); + (void) readl(RSWRST); + + while (1) + ; +}