diff mbox

[U-Boot,1/5] arm: exynos: clean up checkpatch issues

Message ID 5629F087.1070206@samsung.com
State Accepted
Delegated to: Minkyu Kang
Headers show

Commit Message

Minkyu Kang Oct. 23, 2015, 8:32 a.m. UTC 
This patch will fix these checkpatch issues.

ERROR: Macros with complex values should be enclosed in parentheses
+#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)

		ERROR: space prohibited before that ',' (ctx:WxW)
+	writel(val , &drex0->concontrol);
 	           ^

ERROR: space prohibited before that ',' (ctx:WxW)
+	writel(val , &drex1->concontrol);
    	           ^

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
---
 arch/arm/mach-exynos/dmc_init_ddr3.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Minkyu Kang Nov. 2, 2015, 5:38 a.m. UTC | #1 
On 23/10/15 17:32, Minkyu Kang wrote:
> This patch will fix these checkpatch issues.
> 
> ERROR: Macros with complex values should be enclosed in parentheses
> +#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
> +				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
> 
> 		ERROR: space prohibited before that ',' (ctx:WxW)
> +	writel(val , &drex0->concontrol);
>  	           ^
> 
> ERROR: space prohibited before that ',' (ctx:WxW)
> +	writel(val , &drex1->concontrol);
>     	           ^
> 
> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
> ---
>  arch/arm/mach-exynos/dmc_init_ddr3.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.
diff mbox

Patch

diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 7c0b12a..25a9df9 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -20,8 +20,8 @@ 
 #define TIMEOUT_US		10000
 #define NUM_BYTE_LANES		4
 #define DEFAULT_DQS		8
-#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
-				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
+#define DEFAULT_DQS_X4		((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0))
 
 #ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
@@ -856,10 +856,10 @@  int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 	 */
 	val = readl(&drex0->concontrol);
 	val |= CONCONTROL_UPDATE_MODE;
-	writel(val , &drex0->concontrol);
+	writel(val, &drex0->concontrol);
 	val = readl(&drex1->concontrol);
 	val |= CONCONTROL_UPDATE_MODE;
-	writel(val , &drex1->concontrol);
+	writel(val, &drex1->concontrol);
 
 	return 0;
 }