From patchwork Wed Feb 18 06:13:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 440805 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 695781400DD for ; Wed, 18 Feb 2015 17:13:54 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E8B664B61A; Wed, 18 Feb 2015 07:13:51 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BbxWUjymCNPy; Wed, 18 Feb 2015 07:13:51 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 66D2A4A049; Wed, 18 Feb 2015 07:13:51 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5F8B54A049 for ; Wed, 18 Feb 2015 07:13:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lUzoFOaHOS-9 for ; Wed, 18 Feb 2015 07:13:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from thoth.sbs.de (thoth.sbs.de [192.35.17.2]) by theia.denx.de (Postfix) with ESMTPS id 22EF34A03F for ; Wed, 18 Feb 2015 07:13:45 +0100 (CET) Received: from mail2.siemens.de (localhost [127.0.0.1]) by thoth.sbs.de (8.14.3/8.14.3) with ESMTP id t1I6DeuS006156; Wed, 18 Feb 2015 07:13:40 +0100 Received: from md1f2u6c.ww002.siemens.net ([139.22.41.87]) by mail2.siemens.de (8.14.3/8.14.3) with SMTP id t1I6Dd3p007548; Wed, 18 Feb 2015 07:13:39 +0100 Message-ID: <54E42D93.2090809@siemens.com> Date: Wed, 18 Feb 2015 07:13:39 +0100 From: Jan Kiszka User-Agent: Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 MIME-Version: 1.0 To: Stephen Warren , U-Boot Mailing List , Tom Warren , Thierry Reding References: <48840a4f6b07a748ff10c20ffa69f6732c967b35.1424091289.git.jan.kiszka@siemens.com> <54E3AC95.7070200@wwwdotorg.org> In-Reply-To: <54E3AC95.7070200@wwwdotorg.org> Cc: Paul Walmsley , Ian Campbell Subject: Re: [U-Boot] [PATCH v2 09/12] tegra124: Add PSCI support for Tegra124 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On 2015-02-17 22:03, Stephen Warren wrote: > On 02/16/2015 05:54 AM, Jan Kiszka wrote: >> This is based on Thierry Reding's work and uses Ian Campell's >> preparatory patches. It comes with full support for CPU_ON/OFF PSCI >> services. The algorithm used in this version for turning CPUs on and >> off was proposed by Thierry Reding in >> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It >> consists of first enabling CPU1..3 via the PMC, just to powergate them >> again with the help of the Flow Controller. Once the Flow Controller is >> in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF >> PSCI requests. > >> diff --git a/arch/arm/cpu/armv7/tegra124/ap.c >> b/arch/arm/cpu/armv7/tegra124/ap.c > >> +void ap_pm_init(void) >> +{ >> + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; >> + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; >> + >> + writel((u32)park_cpu, EXCEP_VECTOR_CPU_RESET_VECTOR); >> + >> + tegra_powergate_power_on(TEGRA_POWERGATE_CPU1); >> + tegra_powergate_power_on(TEGRA_POWERGATE_CPU2); >> + tegra_powergate_power_on(TEGRA_POWERGATE_CPU3); >> + >> + writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); >> + writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); >> + writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); >> + >> + writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); >> + writel(EVENT_MODE_STOP, &flow->halt_cpu2_events); >> + writel(EVENT_MODE_STOP, &flow->halt_cpu3_events); > > I would expect to set up halt_cpu*_events before powering on the CPUs, > to make sure that they do the expected action on the very first WFI. So, > shouldn't the order above be: > > Write to halt_cpu*_events > Write to cpu*_csr > power_on Yeah, that was my original expectation as well. But doesn't work in practice. I suspect the power-on overwrites what the flow controller configures in the PMC beforehand. But maybe someone can explain this better than me. Jan diff --git a/arch/arm/cpu/armv7/tegra124/ap.c b/arch/arm/cpu/armv7/tegra124/ap.c index eebc0ea..240c71d 100644 --- a/arch/arm/cpu/armv7/tegra124/ap.c +++ b/arch/arm/cpu/armv7/tegra124/ap.c @@ -25,10 +25,6 @@ void ap_pm_init(void) writel((u32)park_cpu, EXCEP_VECTOR_CPU_RESET_VECTOR); - tegra_powergate_power_on(TEGRA_POWERGATE_CPU1); - tegra_powergate_power_on(TEGRA_POWERGATE_CPU2); - tegra_powergate_power_on(TEGRA_POWERGATE_CPU3); - writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); @@ -37,6 +33,10 @@ void ap_pm_init(void) writel(EVENT_MODE_STOP, &flow->halt_cpu2_events); writel(EVENT_MODE_STOP, &flow->halt_cpu3_events); + tegra_powergate_power_on(TEGRA_POWERGATE_CPU1); + tegra_powergate_power_on(TEGRA_POWERGATE_CPU2); + tegra_powergate_power_on(TEGRA_POWERGATE_CPU3); + while (readl(&pmc->pmc_pwrgate_status) & ((1 << TEGRA_POWERGATE_CPU1) | (1 << TEGRA_POWERGATE_CPU2) | (1 << TEGRA_POWERGATE_CPU3)))