From patchwork Sun Oct 18 14:11:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 1383838 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CDhdv3PCRz9sTK for ; Mon, 19 Oct 2020 01:11:45 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8CFAA81F7C; Sun, 18 Oct 2020 16:11:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id BCF9F8236F; Sun, 18 Oct 2020 16:11:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mx.tkos.co.il (guitar.tcltek.co.il [192.115.133.116]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 16F5781F7C for ; Sun, 18 Oct 2020 16:11:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=baruch@tkos.co.il Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id B29F4440CDB; Sun, 18 Oct 2020 17:11:16 +0300 (IDT) From: Baruch Siach To: u-boot@lists.denx.de, Stefan Roese Cc: Grzegorz Jaszczyk , Luka Kovacic Subject: [PATCH 3/3] phy: marvell: cp110: update mode parameter for pcie power on calls Date: Sun, 18 Oct 2020 17:11:13 +0300 Message-Id: <51ce3568cc48c58c859543e7ccd10fc36d537f64.1603027887.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Igal Liberman It helps ATF to determine who called power on function (U-boot/Linux). The corresponding ATF code was added in this commit: mvebu: cp110: avoid pcie power on/off sequence when called from Linux https://github.com/ARM-software/arm-trusted-firmware/commit/55df84f974ea37abbb4f93f000f101f70cda5303 Signed-off-by: Igal Liberman Reviewed-by: Grzegorz Jaszczyk Signed-off-by: Baruch Siach --- drivers/phy/marvell/comphy_cp110.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 5b6aaa62487b..b0fcb13f1c9a 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -28,13 +28,16 @@ DECLARE_GLOBAL_DATA_PTR; #define MV_SIP_COMPHY_POWER_OFF 0x82000002 #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 +/* Used to distinguish between different possible callers (U-boot/Linux) */ +#define COMPHY_CALLER_UBOOT (0x1 << 21) + #define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) #define COMPHY_FW_FORMAT(mode, idx, speeds) \ (((mode) << 12) | ((idx) << 8) | ((speeds) << 2)) #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ - (((pcie_width) << 18) | ((clk_src) << 17) | \ - COMPHY_FW_FORMAT(mode, 0, speeds)) + (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \ + ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds)) #define COMPHY_SATA_MODE 0x1 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */