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Thu, 22 Nov 2012 13:22:44 +0900 (KST) Received: from [10.90.51.55] by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDV00I6UG5WQP60@mmp2.samsung.com> for u-boot@lists.denx.de; Thu, 22 Nov 2012 13:22:44 +0900 (KST) Message-id: <50ADA88E.9020508@samsung.com> Date: Thu, 22 Nov 2012 13:22:38 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:16.0) Gecko/20121011 Thunderbird/16.0.1 MIME-version: 1.0 To: "u-boot@lists.denx.de" DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkkeLIzCtJLcpLzFFi42I5/e+Znu6UFWsDDI7/tLF4u7eT3YHR4+yd HYwBjFFcNimpOZllqUX6dglcGbf2hxecVqxofNfG2MD4V6qLkYNDQsBE4m+rchcjJ5ApJnHh 3nq2LkYuDiGBZYwSP1/3MUEkTCTaJp2GSkxnlNj+7x07hNPEJHHy8xQ2kEm8AloSNw/ogzSw CKhKzL68HKyZTUBHYvu340wgJaICYRI7N6eDhHkFBCV+TL7HAmKLCBhK/N29G8xmFtjPKNH2 shLEFhawk3ixYwMTRFxHYn/rNDYIW15i85q3zBCrBCS+TT7EAvGLrMSmA8wgl0kIvGaTuHr0 AivE/ZISB1fcYJnAKDILyepZSMbOQjJ2ASPzKkbR1ILkguKk9FwjveLE3OLSvHS95PzcTYyQ 8JbewbiqweIQowAHoxIPb4bB2gAh1sSy4srcQ4wSHMxKIryLCoBCvCmJlVWpRfnxRaU5qcWH GH2Arp3ILCWanA+MvbySeENjA2NDQ0tDM1NLUwMcwkrivM0eKQFCAumJJanZqakFqUUw45g4 OKUaGJv2xj3vtj+2iO3gQmXtJccTdnAU/K0+Knfq1xxb/pjgXCmJiN8CLy7q1Ww6/maO54Q5 rN9ld2jMWc8UGhcXe0aiIX/toRV6CyqeZU3NLjWW+f9V4mf5l4xVcsUca7ZVBu/t8nux4eC+ DllXa+nW2BNvly40DK8TCKkr+8AQeIf12c2SMOeeH0osxRmJhlrMRcWJAAoo1kOcAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsVy+t9jQd0pK9YGGMx/ZmTxdm8nuwOjx9k7 OxgDGKMaGG0yUhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTyEnNTbZVcfAJ03TJz gMYqKZQl5pQChQISi4uV9O0wTQgNcdO1gGmM0PUNCYLrMTJAAwnrGDNu7Q8vOK1Y0fiujbGB 8a9UFyMnh4SAiUTbpNNsELaYxIV764FsLg4hgemMEtv/vWOHcJqYJE5+ngKU4eDgFdCSuHlA H6SBRUBVYvbl5UwgNpuAjsT2b8eZQEpEBcIkdm5OBwnzCghK/Jh8jwXEFhEwlPi7ezeYzSyw n1Gi7WUliC0sYCfxYscGJoi4jsT+1mlsELa8xOY1b5knMPLNQjJqFpKyWUjKFjAyr2IUTS1I LihOSs810itOzC0uzUvXS87P3cQIjp9n0jsYVzVYHGIU4GBU4uHNMFgbIMSaWFZcmXuIUYKD WUmEd1EBUIg3JbGyKrUoP76oNCe1+BCjD9CjE5mlRJPzgbGdVxJvaGxiZmRpZGZsYm5sjENY SZy32SMlQEggPbEkNTs1tSC1CGYcEwenVAOj8T/7Ov/FvnmOrzdLc93ckfpbov2FjMqv0qUi zVtr1TwXmfM/up7r+0Dz/1QhGQ0fRYc/yT9kfwcb5zXYvghwm118XSaj1sks/m1SjKsWY5fI 3jQhibla+pdDzzVns6gdMeHffunEir0Hz/5nOsJaZDZbpMbCha93pciHJZrcNS6xFl8SDiux FGckGmoxFxUnAgAnJwR/zAIAAA== X-CFilter-Loop: Reflected Cc: Kyungmin Park , Rajeshwari Shinde Subject: [U-Boot] [PATCH] Exynos: clock: support get_mmc_clk for exynos X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park --- arch/arm/cpu/armv7/exynos/clock.c | 107 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 108 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fe61f88..731bbff 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -373,6 +373,100 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +static unsigned long exynos4_get_mmc_clk(int dev_index) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio, pre_ratio; + int shift; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + switch (dev_index) { + case 0: + case 1: + ratio = readl(&clk->div_fsys1); + pre_ratio = readl(&clk->div_fsys1); + break; + case 2: + case 3: + ratio = readl(&clk->div_fsys2); + pre_ratio = readl(&clk->div_fsys2); + break; + case 4: + ratio = readl(&clk->div_fsys3); + pre_ratio = readl(&clk->div_fsys3); + break; + default: + return 0; + } + + if (dev_index == 1 || dev_index == 3) + shift = 16; + + ratio = (ratio >> shift) & 0xf; + pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; + uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); + + return uclk; +} + +static unsigned long exynos5_get_mmc_clk(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio, pre_ratio; + int shift; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + switch (dev_index) { + case 0: + case 1: + ratio = readl(&clk->div_fsys1); + pre_ratio = readl(&clk->div_fsys1); + break; + case 2: + case 3: + ratio = readl(&clk->div_fsys2); + pre_ratio = readl(&clk->div_fsys2); + break; + default: + return 0; + } + + if (dev_index == 1 || dev_index == 3) + shift = 16; + + ratio = (ratio >> shift) & 0xf; + pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; + uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -386,9 +480,14 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] * CLK_DIV_FSYS2 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8] */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; + } else if (dev_index == 4) { + addr = (unsigned int)&clk->div_fsys3; + dev_index -= 4; } else { addr = (unsigned int)&clk->div_fsys2; dev_index -= 2; @@ -963,6 +1062,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); } +unsigned long get_mmc_clk(int dev_index) +{ + if (cpu_is_exynos5()) + return exynos5_get_mmc_clk(dev_index); + else + return exynos4_get_mmc_clk(dev_index); +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cd12323..ff155d8 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -34,6 +34,7 @@ unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); +unsigned long get_mmc_clk(int deV_index); void set_mmc_clk(int dev_index, unsigned int div); unsigned long get_lcd_clk(void); void set_lcd_clk(void);