Message ID | 4a029fae-c5f8-bcfa-14e4-c5b636351e32@mclink.it |
---|---|
State | Changes Requested |
Delegated to: | Peng Fan |
Headers | show |
Series | [RFC] Vocore2 MMC needs clock patches | expand |
On Tue, 2020-01-21 at 00:55 +0100, Mauro Condarelli wrote: > Hi Weijie, > I attach my, apparently working, port to VoCore2 SoM. > > These patchsets are on top of Your 21 patch rewrite of MT7628 board, > > While the first patchset is relatively straightforward, but does not include > MMC handling, to enable it I had to backport from Linux Kernel several > pieces, essentially clock and interrupt handling. You are using a superseded patch series (v1) I submitted several months ago. These patches have already been replaced by v3 and merged into the mainline. * "mtmips-clk-gate" from v1 is replaced by "mediatek,mt7628-clk" and the function of "mediatek,mt7628-clk" is a superset of "mtmips-clk-gate". * The node "intc" has no use at all. U-Boot for mips use no interrupts. * mmc property "hclk" is the gating clock of the SD controller module. Using <&clk48m> in the v1 patches was a bad idea. I changed it to <&clkctrl CLK_SDXC> in v3 to make sure its clock will be always enabled. * Please move pinctrl properties to your board's dts file. * pinctrl name "state_uhs" is not used by mtk-sd in U-Boot. MT7628 does not support UHS. You should remove it. * vmmc-supply and vqmmc-supply are not used by mtk-sd in U-Boot because UHS support is not added to the driver. Besides you have assigned wrong values to them. You should remove it. > > Those drivers appear written by You. > I am unsure if this is really needed or if there is some other (perhaps > cleaner) > way to enable MMC. > > As said this seems to work for me, but I would like to contribute this > board upstream, in the best possible way. > > Please let me know how I should proceed. I don't have a board with the "sd_iot_mode" pinmux for SDXC, so I can't tell you why you can't use it with my v3 patches. But I have tested v3 patches on boards using "sd_router_mode" pinmux and they do work well. > > Best Regards and Thanks in Advance > >
Thanks Weijie, I made the changes You suggested. I have also seen You sent a new version of Your patches. Since mine are based on yours I *think* I should suspend sending my VoCore2 patches till Yours are fixed and integrated into master. @Stefan Roese: is this the right course of action? I am happy what I have (pending further test, of course!), but I want this integrated in upstream master, if possible, so I'm prepared to rebase my patches after Weijie ones are in. Any comment welcome. Side Question: Stefan wrote: > Most of this can be done by using the > RAM version now (again). There is no additional RAM booting target now > any more. You can use the normal U-Boot image for this now. Please note > the changes TEXT_BASE here. Its now 0x80200000. This actually seems to work right if I start from my original u-boot (1.1.3, flashed at start of SPI NOR), but it fails if I start from a flashed (at the same location) u-boot-mtmips.bin I *think* this happens because unpacking actually writes u-boot at 0x80200000 and runs it from there, so "load usb 0:1 80200000 u-boot.bin" (or equivalent) will overwrite the running u-boot and the following "go ${fileaddr}" fails: ## Starting application at 0x80200000 ... <DEAD> Note that if I load the same version flashed it works ok (presumably because I'm overwriting with the same content, so no harm done). How can I load in RAM end test a new version once I flash new-style u-boot? I am thinking about relinking at a different address, but I'm unsure. TiA! Regards Mauro Condarelli On 1/21/20 4:11 AM, Weijie Gao wrote: > On Tue, 2020-01-21 at 00:55 +0100, Mauro Condarelli wrote: >> Hi Weijie, >> I attach my, apparently working, port to VoCore2 SoM. >> >> These patchsets are on top of Your 21 patch rewrite of MT7628 board, >> >> While the first patchset is relatively straightforward, but does not include >> MMC handling, to enable it I had to backport from Linux Kernel several >> pieces, essentially clock and interrupt handling. > You are using a superseded patch series (v1) I submitted several months > ago. These patches have already been replaced by v3 and merged into the > mainline. > > * "mtmips-clk-gate" from v1 is replaced by "mediatek,mt7628-clk" and the > function of "mediatek,mt7628-clk" is a superset of "mtmips-clk-gate". > * The node "intc" has no use at all. U-Boot for mips use no interrupts. > * mmc property "hclk" is the gating clock of the SD controller module. > Using <&clk48m> in the v1 patches was a bad idea. I changed it to > <&clkctrl CLK_SDXC> in v3 to make sure its clock will be always > enabled. > * Please move pinctrl properties to your board's dts file. > * pinctrl name "state_uhs" is not used by mtk-sd in U-Boot. MT7628 does > not support UHS. You should remove it. > * vmmc-supply and vqmmc-supply are not used by mtk-sd in U-Boot because > UHS support is not added to the driver. Besides you have assigned > wrong values to them. You should remove it. > >> Those drivers appear written by You. >> I am unsure if this is really needed or if there is some other (perhaps >> cleaner) >> way to enable MMC. >> >> As said this seems to work for me, but I would like to contribute this >> board upstream, in the best possible way. >> >> Please let me know how I should proceed. > I don't have a board with the "sd_iot_mode" pinmux for SDXC, so I can't > tell you why you can't use it with my v3 patches. But I have tested v3 > patches on boards using "sd_router_mode" pinmux and they do work well. > >> Best Regards and Thanks in Advance >> >>
Hi Mauro, On 21.01.20 12:27, Mauro Condarelli wrote: > Thanks Weijie, > I made the changes You suggested. > I have also seen You sent a new version of Your patches. > Since mine are based on yours I *think* I should suspend > sending my VoCore2 patches till Yours are fixed and integrated > into master. > > @Stefan Roese: is this the right course of action? I think in the current state of Weijie's patches (v3), you can resume sending your VoCore2 support based on this latest patchset to the list. Please don't attach a patch but send it inline next time (git send-email) to enable review. > I am happy what I have (pending further test, of course!), > but I want this integrated in upstream master, if possible, > so I'm prepared to rebase my patches after Weijie ones > are in. > > Any comment welcome. > > Side Question: Stefan wrote: >> Most of this can be done by using the >> RAM version now (again). There is no additional RAM booting target now >> any more. You can use the normal U-Boot image for this now. Please note >> the changes TEXT_BASE here. Its now 0x80200000. > This actually seems to work right if I start from my original u-boot > (1.1.3, > flashed at start of SPI NOR), but it fails if I start from a flashed (at the > same location) u-boot-mtmips.bin > I *think* this happens because unpacking actually writes u-boot at > 0x80200000 and runs it from there, so "load usb 0:1 80200000 u-boot.bin" > (or equivalent) will overwrite the running u-boot and the following > "go ${fileaddr}" fails: > ## Starting application at 0x80200000 ... > <DEAD> No, U-Boot relocates itself to the end of RAM and runs from there. So this should work. Perhaps a cache flush is missing. I'll give it a try on my LinkIt board as well later. > Note that if I load the same version flashed it works ok (presumably because > I'm overwriting with the same content, so no harm done). > How can I load in RAM end test a new version once I flash new-style u-boot? > I am thinking about relinking at a different address, but I'm unsure. See above. Thanks, Stefan
Hi Stefan, On 1/21/20 1:08 PM, Stefan Roese wrote: > Hi Mauro, > > On 21.01.20 12:27, Mauro Condarelli wrote: >> Thanks Weijie, >> I made the changes You suggested. >> I have also seen You sent a new version of Your patches. >> Since mine are based on yours I *think* I should suspend >> sending my VoCore2 patches till Yours are fixed and integrated >> into master. >> >> @Stefan Roese: is this the right course of action? > > I think in the current state of Weijie's patches (v3), you can resume > sending your VoCore2 support based on this latest patchset to the > list. Please don't attach a patch but send it inline next time > (git send-email) to enable review. I will send next iteration as soon as I fix the reflash problem (see below). ===8<---- >> Side Question: Stefan wrote: >>> Most of this can be done by using the >>> RAM version now (again). There is no additional RAM booting target now >>> any more. You can use the normal U-Boot image for this now. Please note >>> the changes TEXT_BASE here. Its now 0x80200000. >> This actually seems to work right if I start from my original u-boot >> (1.1.3, >> flashed at start of SPI NOR), but it fails if I start from a flashed >> (at the >> same location) u-boot-mtmips.bin >> I *think* this happens because unpacking actually writes u-boot at >> 0x80200000 and runs it from there, so "load usb 0:1 80200000 u-boot.bin" >> (or equivalent) will overwrite the running u-boot and the following >> "go ${fileaddr}" fails: >> ## Starting application at 0x80200000 ... >> <DEAD> > > No, U-Boot relocates itself to the end of RAM and runs from there. So > this should work. Perhaps a cache flush is missing. > > I'll give it a try on my LinkIt board as well later. Did You manage to test this? I am currently testing loading from "paleolithic" u-boot, but I want to fix this before I finalize VoCore2 patches. I tried to do some manual testing enabling CONFIG_CMD_CACHE, but this bombs with Weijie patches with: LD u-boot mipsel-linux-ld.bfd: cmd/built-in.o: in function `do_icache': cmd/cache.c:(.text.do_icache+0x5c): undefined reference to `icache_disable' mipsel-linux-ld.bfd: cmd/cache.c:(.text.do_icache+0x6c): undefined reference to `icache_enable' mipsel-linux-ld.bfd: cmd/cache.c:(.text.do_icache+0x8c): undefined reference to `icache_status' make: *** [Makefile:1697: u-boot] Error 1 icache seems enabled unconditionally in arch/mips/mach-mtmips/mt7628/lowlevel_init.S::73+ I will try to add dummy functions just-to-play. Please advise > Thanks, > Stefan Regards and Many Thanks Mauro
Hi, I'm clearly out of my depth: => icache flush No arch specific invalidate_icache_all available! => dcache flush No arch specific flush_dcache_all available! => icache off => dcache off Ooops: $ 0 : 00000000 00000000 87e806c8 00000000 $ 4 : ffffffd0 00000014 87e80518 87fce61c $ 8 : 87e7bc00 00000010 00000000 fffffffc $12 : 00000000 0000000f 00000006 00000007 $16 : ffffffd0 00000000 00000000 0000002f $20 : 87e81350 87fe8528 00000000 00000001 $24 : 00000016 87f84130 $28 : 87f882a0 87e7bba8 87e81362 87fa9524 Hi : 00000006 Lo : 000640a2 epc : 87fa1600 (text 80221600) ra : 87fa9524 (text 80229524) Status: 00000006 Cause : d0008028 (ExcCode 0a) PrId : 00019655 ### ERROR ### Please RESET the board ### Thanks Mauro On 1/22/20 9:16 PM, Mauro Condarelli wrote: > Hi Stefan, > > On 1/21/20 1:08 PM, Stefan Roese wrote: >> Hi Mauro, >> >> On 21.01.20 12:27, Mauro Condarelli wrote: >>> Thanks Weijie, >>> I made the changes You suggested. >>> I have also seen You sent a new version of Your patches. >>> Since mine are based on yours I *think* I should suspend >>> sending my VoCore2 patches till Yours are fixed and integrated >>> into master. >>> >>> @Stefan Roese: is this the right course of action? >> I think in the current state of Weijie's patches (v3), you can resume >> sending your VoCore2 support based on this latest patchset to the >> list. Please don't attach a patch but send it inline next time >> (git send-email) to enable review. > I will send next iteration as soon as I fix the reflash problem (see below). > > ===8<---- >>> Side Question: Stefan wrote: >>>> Most of this can be done by using the >>>> RAM version now (again). There is no additional RAM booting target now >>>> any more. You can use the normal U-Boot image for this now. Please note >>>> the changes TEXT_BASE here. Its now 0x80200000. >>> This actually seems to work right if I start from my original u-boot >>> (1.1.3, >>> flashed at start of SPI NOR), but it fails if I start from a flashed >>> (at the >>> same location) u-boot-mtmips.bin >>> I *think* this happens because unpacking actually writes u-boot at >>> 0x80200000 and runs it from there, so "load usb 0:1 80200000 u-boot.bin" >>> (or equivalent) will overwrite the running u-boot and the following >>> "go ${fileaddr}" fails: >>> ## Starting application at 0x80200000 ... >>> <DEAD> >> No, U-Boot relocates itself to the end of RAM and runs from there. So >> this should work. Perhaps a cache flush is missing. >> >> I'll give it a try on my LinkIt board as well later. > Did You manage to test this? > I am currently testing loading from "paleolithic" u-boot, but I want to fix > this before I finalize VoCore2 patches. > > I tried to do some manual testing enabling CONFIG_CMD_CACHE, but this > bombs with Weijie patches with: > > LD u-boot > mipsel-linux-ld.bfd: cmd/built-in.o: in function `do_icache': > cmd/cache.c:(.text.do_icache+0x5c): undefined reference to `icache_disable' > mipsel-linux-ld.bfd: cmd/cache.c:(.text.do_icache+0x6c): undefined > reference to `icache_enable' > mipsel-linux-ld.bfd: cmd/cache.c:(.text.do_icache+0x8c): undefined > reference to `icache_status' > make: *** [Makefile:1697: u-boot] Error 1 > > icache seems enabled unconditionally in > arch/mips/mach-mtmips/mt7628/lowlevel_init.S::73+ > > I will try to add dummy functions just-to-play. > > Please advise > >> Thanks, >> Stefan > Regards and Many Thanks > Mauro >
Hi Maruo, On 22.01.20 21:16, Mauro Condarelli wrote: > Hi Stefan, > > On 1/21/20 1:08 PM, Stefan Roese wrote: >> Hi Mauro, >> >> On 21.01.20 12:27, Mauro Condarelli wrote: >>> Thanks Weijie, >>> I made the changes You suggested. >>> I have also seen You sent a new version of Your patches. >>> Since mine are based on yours I *think* I should suspend >>> sending my VoCore2 patches till Yours are fixed and integrated >>> into master. >>> >>> @Stefan Roese: is this the right course of action? >> >> I think in the current state of Weijie's patches (v3), you can resume >> sending your VoCore2 support based on this latest patchset to the >> list. Please don't attach a patch but send it inline next time >> (git send-email) to enable review. > I will send next iteration as soon as I fix the reflash problem (see below). > > ===8<---- >>> Side Question: Stefan wrote: >>>> Most of this can be done by using the >>>> RAM version now (again). There is no additional RAM booting target now >>>> any more. You can use the normal U-Boot image for this now. Please note >>>> the changes TEXT_BASE here. Its now 0x80200000. >>> This actually seems to work right if I start from my original u-boot >>> (1.1.3, >>> flashed at start of SPI NOR), but it fails if I start from a flashed >>> (at the >>> same location) u-boot-mtmips.bin >>> I *think* this happens because unpacking actually writes u-boot at >>> 0x80200000 and runs it from there, so "load usb 0:1 80200000 u-boot.bin" >>> (or equivalent) will overwrite the running u-boot and the following >>> "go ${fileaddr}" fails: >>> ## Starting application at 0x80200000 ... >>> <DEAD> >> >> No, U-Boot relocates itself to the end of RAM and runs from there. So >> this should work. Perhaps a cache flush is missing. >> >> I'll give it a try on my LinkIt board as well later. > Did You manage to test this? Yes. I just tested for a few minutes and it seems to work on the LinkIt board: => printenv tt tt=tftp 80200000 ${tftpdir}/u-boot.bin;dcache off;go ${fileaddr} => run tt Using eth@10110000 device TFTP from server 192.168.1.5; our IP address is 192.168.1.233 Filename 'linkit-smart-7688/u-boot.bin'. Load address: 0x80200000 Loading: ############################### 4.8 MiB/s done Bytes transferred = 450139 (6de5b hex) Unknown command 'dcache' - try 'help' ## Starting application at 0x80200000 ... U-Boot 2020.01-00680-g90cb39245e (Jan 21 2020 - 10:54:50 +0100) CPU: MediaTek MT7688A ver:1 eco:2 Boot: DDR2, SPI-NOR 4-Byte Addr, CPU clock from XTAL Clock: CPU: 580MHz, Bus: 193MHz, XTAL: 40MHz Model: LinkIt-Smart-7688 ... > I am currently testing loading from "paleolithic" u-boot, but I want to fix > this before I finalize VoCore2 patches. > > I tried to do some manual testing enabling CONFIG_CMD_CACHE, but this > bombs with Weijie patches with: > > LD u-boot > mipsel-linux-ld.bfd: cmd/built-in.o: in function `do_icache': > cmd/cache.c:(.text.do_icache+0x5c): undefined reference to `icache_disable' > mipsel-linux-ld.bfd: cmd/cache.c:(.text.do_icache+0x6c): undefined > reference to `icache_enable' > mipsel-linux-ld.bfd: cmd/cache.c:(.text.do_icache+0x8c): undefined > reference to `icache_status' > make: *** [Makefile:1697: u-boot] Error 1 > > icache seems enabled unconditionally in > arch/mips/mach-mtmips/mt7628/lowlevel_init.S::73+ > > I will try to add dummy functions just-to-play. No need to "play" with these cache functions. Its included in the LinkIt image and should be in yours as well, if you didn't change too much. Thanks, Stefan
From 602ac7d1424ce500e7c818431d7aa8aa97b654f2 Mon Sep 17 00:00:00 2001 From: Mauro Condarelli <mc5686@mclink.it> Date: Tue, 21 Jan 2020 00:37:43 +0100 Subject: [PATCH 2/2] mips: mtmips: vocore2: add support for MMC/SD Signed-off-by: Mauro Condarelli <mc5686@mclink.it> --- arch/mips/dts/mt7628a.dtsi | 48 ++++++++++++++++++++- configs/vocore2_defconfig | 10 ++++- drivers/clk/Kconfig | 8 ++++ drivers/clk/Makefile | 1 + drivers/clk/clk-mtmips-cg.c | 63 ++++++++++++++++++++++++++++ drivers/phy/Kconfig | 2 + include/configs/vocore2.h | 22 +++++----- include/dt-bindings/clk/mt7628-clk.h | 31 ++++++++++++++ 8 files changed, 172 insertions(+), 13 deletions(-) create mode 100644 drivers/clk/clk-mtmips-cg.c create mode 100644 include/dt-bindings/clk/mt7628-clk.h diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index f265cb6ad9..a47309732a 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -7,6 +7,18 @@ #size-cells = <1>; compatible = "ralink,mt7628a-soc"; + resetc: reset-controller { + compatible = "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + clk48m: clk48m@0 { compatible = "fixed-clock"; @@ -41,6 +53,12 @@ u-boot,dm-pre-reloc; }; + clkgate: clkgate@0x30 { + reg = <0x30 0x4>; + compatible = "mediatek,mtmips-clk-gate"; + #clock-cells = <1>; + }; + rstctrl: rstctrl@0x34 { reg = <0x34 0x4>; compatible = "mediatek,mtmips-reset"; @@ -213,6 +231,24 @@ reset-names = "wdt"; }; + intc: interrupt-controller@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&resetc 9>; + reset-names = "intc"; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + ralink,intc-registers = <0x9c 0xa0 + 0x6c 0xa4 + 0x80 0x78>; + }; + gpio@600 { #address-cells = <1>; #size-cells = <0>; @@ -346,9 +382,19 @@ builtin-cd = <1>; r_smpl = <1>; - clocks = <&clk48m>, <&clkctrl CLK_SDXC>; + interrupt-parent = <&intc>; + interrupts = <14>; + + clocks = <&clk48m>, <&clk48m>; clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd_iot_mode>; + pinctrl-1 = <&sd_iot_mode>; + + vmmc-supply = <&clk48m>; + vqmmc-supply = <&clk48m>; + resets = <&rstctrl MT7628_SDXC_RST>; status = "disabled"; diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index 6cc85ae64a..9758038dd7 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -28,10 +28,12 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PART=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y @@ -43,10 +45,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_SPL_DM=y # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_BLK=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y CONFIG_MTD=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y @@ -57,6 +62,7 @@ CONFIG_SPI_FLASH_MTD=y # CONFIG_DM_ETH is not set CONFIG_PHY=y CONFIG_MT76X8_USB_PHY=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_USB=y @@ -64,6 +70,8 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y CONFIG_FS_EXT4=y CONFIG_LZMA=y CONFIG_LZO=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 16d4237f89..fbe6ae86d6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -176,4 +176,12 @@ config SANDBOX_CLK_CCF Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver. +config CLK_MTMIPS_GATE + bool "Enable clock gating driver for MediaTek MIPS platform" + depends on CLK && ARCH_MTMIPS + default y + help + Enable clock gating driver for MediaTek MIPS platform. + This driver supports only clock enable and disable. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 06131edb9f..585335be25 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk-mtmips-cg.c b/drivers/clk/clk-mtmips-cg.c new file mode 100644 index 0000000000..0221d95aed --- /dev/null +++ b/drivers/clk/clk-mtmips-cg.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> + +struct mtmips_clk_gate_priv { + void __iomem *base; +}; + +static int mtmips_clk_gate_enable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + setbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +static int mtmips_clk_gate_disable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + clrbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mtmips_clk_gate_ops = { + .enable = mtmips_clk_gate_enable, + .disable = mtmips_clk_gate_disable, +}; + +static int mtmips_clk_gate_probe(struct udevice *dev) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_clk_gate_ids[] = { + { .compatible = "mediatek,mtmips-clk-gate" }, + { } +}; + +U_BOOT_DRIVER(mtmips_clk_gate) = { + .name = "mtmips-clk-gate", + .id = UCLASS_CLK, + .of_match = mtmips_clk_gate_ids, + .probe = mtmips_clk_gate_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv), + .ops = &mtmips_clk_gate_ops, +}; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a72f34f0d4..d9acda2c6a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -201,6 +201,8 @@ config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY depends on SOC_MT7628 + select CLK + select DM_RESET help Support the USB PHY in MT76x8 SoCs diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index e90c3c2d74..8006cf8804 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -7,14 +7,14 @@ #define __VOCORE2_CONFIG_H__ /* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) @@ -42,17 +42,17 @@ 230400, 460800, 921600 } /* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 /* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 /* U-Boot */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Environment settings */ #if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) diff --git a/include/dt-bindings/clk/mt7628-clk.h b/include/dt-bindings/clk/mt7628-clk.h new file mode 100644 index 0000000000..6784d6e50b --- /dev/null +++ b/include/dt-bindings/clk/mt7628-clk.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +#define MT7628_PWM_CLK 31 +#define MT7628_SDXC_CLK 30 +#define MT7628_CRYPTO_CLK 29 +#define MT7628_MIPS_CNT_CLK 28 +#define MT7628_PCIE_CLK 26 +#define MT7628_UPHY_CLK 25 +#define MT7628_ETH_CLK 23 +#define MT7628_UART2_CLK 20 +#define MT7628_UART1_CLK 19 +#define MT7628_SPI_CLK 18 +#define MT7628_I2S_CLK 17 +#define MT7628_I2C_CLK 16 +#define MT7628_GDMA_CLK 14 +#define MT7628_PIO_CLK 13 +#define MT7628_UART0_CLK 12 +#define MT7628_PCM_CLK 11 +#define MT7628_MC_CLK 10 +#define MT7628_INT_CLK 9 +#define MT7628_TIMER_CLK 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */ -- 2.25.0