From patchwork Thu Apr 5 06:29:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Donghwa Lee X-Patchwork-Id: 150876 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 83538B7047 for ; Thu, 5 Apr 2012 16:30:13 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A37428141; Thu, 5 Apr 2012 08:29:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZlJU9nf4TXyL; Thu, 5 Apr 2012 08:29:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0F8ED2814B; Thu, 5 Apr 2012 08:29:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8EE0228142 for ; Thu, 5 Apr 2012 08:29:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zJxkOIf71LwP for ; Thu, 5 Apr 2012 08:29:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by theia.denx.de (Postfix) with ESMTP id 5F03528116 for ; Thu, 5 Apr 2012 08:29:28 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTP id <0M1Z00IAXTXDHMR0@mailout3.samsung.com> for u-boot@lists.denx.de; Thu, 05 Apr 2012 15:29:25 +0900 (KST) X-AuditID: cbfee61b-b7baeae000004fa7-ac-4f7d3bc5445b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id 41.AB.20391.5CB3D7F4; Thu, 05 Apr 2012 15:29:25 +0900 (KST) Received: from [165.213.219.92] by mmp2.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTPA id <0M1Z002BCU11DM30@mmp2.samsung.com> for u-boot@lists.denx.de; Thu, 05 Apr 2012 15:29:25 +0900 (KST) Message-id: <4F7D3BC4.4020404@samsung.com> Date: Thu, 05 Apr 2012 15:29:24 +0900 From: Donghwa Lee User-Agent: Mozilla/5.0 (X11; Linux i686; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-version: 1.0 To: u-boot@lists.denx.de, mk7.kang@samsung.com, Anatolij Gustschin , Kyungmin Park , Inki Dae , Donghwa Lee X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No Subject: [U-Boot] [PATCH 3/7] LCD: add data structure for EXYNOS display driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add vidinfo data structure for EXYNOS display driver Signed-off-by: Donghwa Lee Signed-off-by: Kyungmin Park Signed-off-by: Inki Dae Acked-by: Anatolij Gustschin --- include/lcd.h | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 64 insertions(+), 0 deletions(-) diff --git a/include/lcd.h b/include/lcd.h index d95feeb..3d9ef16 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -183,6 +183,70 @@ typedef struct vidinfo { u_long mmio; /* Memory mapped registers */ } vidinfo_t; +#elif defined(CONFIG_EXYNOS_FB) + +enum { + FIMD_RGB_INTERFACE = 1, + FIMD_CPU_INTERFACE = 2, +}; + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_freq; /* Frequency */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel */ + + /* Horizontal control register. Timing from data sheet */ + u_char vl_hspw; /* Horz sync pulse width */ + u_char vl_hfpd; /* Wait before of line */ + u_char vl_hbpd; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vspw; /* Vertical sync pulse width */ + u_char vl_vfpd; /* Wait before of frame */ + u_char vl_vbpd; /* Wait end of frame */ + u_char vl_cmd_allow_len; /* Wait end of frame */ + + void (*cfg_gpio)(void); + void (*backlight_on)(unsigned int onoff); + void (*reset_lcd)(void); + void (*lcd_power_on)(void); + void (*cfg_ldo)(void); + void (*enable_ldo)(unsigned int onoff); + void (*mipi_power)(void); + void (*backlight_reset)(void); + + unsigned int win_id; + unsigned int init_delay; + unsigned int power_on_delay; + unsigned int reset_delay; + unsigned int interface_mode; + unsigned int mipi_enabled; + unsigned int cs_setup; + unsigned int wr_setup; + unsigned int wr_act; + unsigned int wr_hold; + + /* parent clock name(MPLL, EPLL or VPLL) */ + unsigned int pclk_name; + /* ratio value for source clock from parent clock. */ + unsigned int sclk_div; + + unsigned int dual_lcd_enabled; + +} vidinfo_t; + +void init_panel_info(vidinfo_t *vid); + #else typedef struct vidinfo {