From patchwork Wed May 4 14:53:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Steven A. Falco" X-Patchwork-Id: 94052 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 68ED6B6F7C for ; Thu, 5 May 2011 00:54:07 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A0F842809C; Wed, 4 May 2011 16:54:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kQ29AtRhDKEB; Wed, 4 May 2011 16:54:05 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D929E28095; Wed, 4 May 2011 16:54:01 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9AD9428095 for ; Wed, 4 May 2011 16:53:59 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A3rbqtWi7Mk6 for ; Wed, 4 May 2011 16:53:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mlbe2k2.cs.myharris.net (mlbe2k2.cs.myharris.net [137.237.90.89]) by theia.denx.de (Postfix) with ESMTP id 07D3328094 for ; Wed, 4 May 2011 16:53:55 +0200 (CEST) Received: from mail pickup service by mlbe2k2.cs.myharris.net with Microsoft SMTPSVC; Wed, 4 May 2011 10:53:53 -0400 Received: from saf.cs.myharris.net ([137.237.94.251]) by mlbe2k2.cs.myharris.net with Microsoft SMTPSVC(6.0.3790.4675); Wed, 4 May 2011 10:53:51 -0400 Message-ID: <4DC1687E.2040103@harris.com> Date: Wed, 04 May 2011 10:53:50 -0400 From: "Steven A. Falco" User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 To: Stefan Roese , "Eibach, Dirk" , u-boot@lists.denx.de X-OriginalArrivalTime: 04 May 2011 14:53:51.0418 (UTC) FILETIME=[14D4F1A0:01CC0A6B] Cc: "Primatic, Agesino" Subject: [U-Boot] [PATCH v2] PPC405EX CHIP_21 erratum X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de v2: Correct checkpatch errors/warnings re: whitespace, comment style, etc. Move PVR logic out of board config file. Simplify ifdef structure. APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. I've personally seen that happen. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for an example. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom board using CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY. Signed-off-by: Steve Falco Acked-by: Dirk Eibach diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index bf208ad..2f3a802 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -221,6 +221,66 @@ void reconfigure_pll(u32 new_cpu_freq) #endif } +#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA +void +chip_21_errata(void) +{ + /* + * See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that + * sometimes reading the PVR and/or SDR0_ECID results in incorrect + * values. Since the rev-D chip uses the SDR0_ECID bits to control + * internal features, that means the second PCIe or ethernet of an EX + * variant could fail to work. Also, security features of both EX and + * EXr might be incorrectly disabled. + * + * The suggested workaround is as follows (covering rev-C and rev-D): + * + * 1.Read the PVR and SDR0_ECID3. + * + * 2.If the PVR matches an expected Revision C PVR value AND if + * SDR0_ECID3[12:15] is different from PVR[28:31], then – processor is + * Revision C: continue executing the initialization code (no reset + * required). else – go to step 3. + * + * 3.If the PVR matches an expected Revision D PVR value AND if + * SDR0_ECID3[10:11] matches its expected value, then – continue + * executing initialization code, no reset required. else – write + * DBCR0[RST] = 0b11 to generate a SysReset. + */ + + u32 pvr; + u32 pvr_28_31; + u32 ecid3; + u32 ecid3_10_11; + u32 ecid3_12_15; + + /* Step 1: */ + pvr = get_pvr(); + mfsdr(SDR0_ECID3, ecid3); + + /* Step 2: */ + pvr_28_31 = pvr & 0xf; + ecid3_10_11 = (ecid3 >> 20) & 0x3; + ecid3_12_15 = (ecid3 >> 16) & 0xf; + if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) && + (pvr_28_31 != ecid3_12_15)) { + /* No reset required. */ + return; + } + + /* Step 3: */ + if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) && + (ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) { + /* No reset required. */ + return; + } + + /* Reset required. */ + __asm__ __volatile__ ("sync; isync"); + mtspr(SPRN_DBCR0, 0x30000000); +} +#endif + /* * Breath some life into the CPU... * @@ -235,6 +295,10 @@ cpu_init_f (void) u32 val; #endif +#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA + chip_21_errata(); +#endif + reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h index 36d3149..8070385 100644 --- a/arch/powerpc/include/asm/ppc405ex.h +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -43,6 +43,11 @@ #define SDR0_PFC1 0x4101 #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + #define SDR0_SDCS_SDD (0x80000000 >> 31) #define SDR0_SRST_DMC (0x80000000 >> 10) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index f5bf4dd..68f9868 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -974,6 +974,37 @@ #define PVR_5200B 0x80822014 /* + * CHIP_21 Errata + */ +#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0 +#endif + +#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1 +#endif + +#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2 +#endif + +#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3 +#endif + +/* * System Version Register */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 031f8fb..2be1104 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -44,6 +44,12 @@ #endif /* + * CHIP_21 errata - you must set this to match your CPU, else the board + * will not boot. + */ +#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY + +/* * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME kilauea