From patchwork Mon Sep 19 20:13:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergej Stepanov X-Patchwork-Id: 115391 X-Patchwork-Delegate: kim.phillips@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D7B39B6FF5 for ; Tue, 20 Sep 2011 06:34:54 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B4A2B28231; Mon, 19 Sep 2011 22:34:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YosDn8ED3fPj; Mon, 19 Sep 2011 22:34:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4E8FD281A9; Mon, 19 Sep 2011 22:34:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3ECE281A9 for ; Mon, 19 Sep 2011 22:34:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qK-qkn2wxoSM for ; Mon, 19 Sep 2011 22:34:42 +0200 (CEST) X-Greylist: delayed 1209 seconds by postgrey-1.27 at theia; Mon, 19 Sep 2011 22:34:40 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ares.ids.de (ares.ids.de [88.79.252.171]) by theia.denx.de (Postfix) with ESMTP id 3D20128124 for ; Mon, 19 Sep 2011 22:34:40 +0200 (CEST) Received: from ares.ids.de (ares.ids.de [127.0.0.1]) by ares.ids.de (PGP Universal) with ESMTP id 5E21EF49239 for ; Mon, 19 Sep 2011 22:14:31 +0200 (CEST) Received: from HERMES2.ids.de ([192.168.0.115]) by ares.ids.de (PGP Universal service); Mon, 19 Sep 2011 22:14:31 +0200 X-PGP-Universal: processed; by ares.ids.de on Mon, 19 Sep 2011 22:14:31 +0200 Received: from HERMES2.ids.de ([127.0.0.1]) by HERMES2 ([127.0.0.1]) with mapi; Mon, 19 Sep 2011 22:13:32 +0200 From: To: Date: Mon, 19 Sep 2011 22:13:31 +0200 Thread-Topic: [PATCH] Add support for IDS8313 boards Thread-Index: AQHMdwaP65WnrZrCOES47kLwPzZReA== Message-ID: <4206182445660643B9AEB8D4E55BBD0A15399F40A4@HERMES2> Accept-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: de-DE MIME-Version: 1.0 Content-Language: de-DE Cc: Rolf.Riehle@ids.de Subject: [U-Boot] [PATCH] Add support for IDS8313 boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds support for IDS8313 boards based on MPC8313 It contains the following components: - both of TSEC's, NOR- and NAND flash, I2C, SPI Signed-off-by: Sergej Stepanov Signed-off-by: Rolf Riehle --- board/ids/ids8313/Makefile | 52 ++++ board/ids/ids8313/ids8313.c | 179 ++++++++++++++ boards.cfg | 1 + include/configs/IDS8313.h | 575 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 807 insertions(+), 0 deletions(-) diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile new file mode 100644 index 0000000..4bd325b --- /dev/null +++ b/board/ids/ids8313/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (c) 2011 IDS GmbH, Germany +# +# Sergej Stepanov +# Based on board/freescale/mpc8313erdb/Makefile +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c new file mode 100644 index 0000000..0d587bb --- /dev/null +++ b/board/ids/ids8313/ids8313.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2011 IDS GmbH, Germany + * ids8313.c -- IDS ids8313 board support. + * + * Sergej Stepanov + * Based on board/freescale/mpc8313erdb/mpc8313erdb.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +extern void disable_addr_trans (void); +extern void enable_addr_trans (void); +int fixed_sdram(void); + +int checkboard (void) +{ + puts("Board: CX73X\n"); + return 0; +} + +phys_size_t initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbc_t *lbc = &im->im_lbc; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + msize = fixed_sdram(); + + /* nado */ + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + sync(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE << 20; + +#if (CONFIG_SYS_DDR_SIZE != 128) +#warning Currently any ddr size other than 256 is not supported +#endif + +#ifndef CONFIG_SYS_RAMBOOT + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + sync(); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG); + + /* currently we use only one CS, so disable the other banks */ + out_be32(&im->ddr.cs_config[1], 0); + out_be32(&im->ddr.cs_config[2], 0); + out_be32(&im->ddr.cs_config[3], 0); + + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); + + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + sync(); + udelay(300); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + /* now check the real size */ + disable_addr_trans (); + msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans (); +#endif + return msize; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif + +#define IDSCPLD_SPI_CS_MASK 0x00000001 +#define IDSCPLD_SPI_BUS_DEFAULT 2 +#define IDSCPLD_SPI_CS_BASE 0xE300000f + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8*)IDSCPLD_SPI_CS_BASE; + + *spi_base = 0; + iopd->dir |= IDSCPLD_SPI_CS_MASK; + return 0; +} +#endif + +#ifdef CONFIG_MPC8XXX_SPI +/* + * The following are used to control the SPI chip selects + */ + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && ((cs>=0)&&(cs<=2)); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8*)IDSCPLD_SPI_CS_BASE; + + *spi_base = (u8)1 << slave->cs; + iopd->dat &= ~IDSCPLD_SPI_CS_MASK; + sync(); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8*)IDSCPLD_SPI_CS_BASE; + + *spi_base = (u8)1 << slave->cs; + iopd->dat |= IDSCPLD_SPI_CS_MASK; + sync(); +} +#endif /* CONFIG_HARD_SPI */ diff --git a/boards.cfg b/boards.cfg index 8a5bfc1..acec06b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -536,6 +536,7 @@ suvd3 powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc tuda1 powerpc mpc83xx km83xx keymile tuxa1 powerpc mpc83xx km83xx keymile +IDS8313 powerpc mpc83xx ids8313 ids - IDS8313:SYS_TEXT_BASE=0xFFF00000 sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/IDS8313.h b/include/configs/IDS8313.h new file mode 100644 index 0000000..9aa3f24 --- /dev/null +++ b/include/configs/IDS8313.h @@ -0,0 +1,575 @@ + +/* + * Copyright (c) 2011 IDS GmbH, Germany + * Sergej Stepanov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC831x 1 +#define CONFIG_MPC8313 1 +#define CONFIG_IDS8313 1 + +#define CONFIG_FSL_ELBC 1 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY +#define CONFIG_AUTOBOOT_DELAY_STR "ids" +#define CONFIG_BOOT_RETRY_TIME 900 +#define CONFIG_BOOT_RETRY_MIN 30 + +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xF0000000 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.000MHz, then + * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz? + */ +#define CONFIG_SYS_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#define CONFIG_SYS_HRCW_HIGH ( HRCWH_PCI_HOST |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_8BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_MII |\ + HRCWH_TSEC2M_IN_MII |\ + HRCWH_BIG_ENDIAN) + +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) + +#define CONFIG_HWCONFIG + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) + +#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) + +/*--------------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DCACHE ) + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ + (0xFF << LBCR_BMT_SHIFT) |\ + 0xF ) + +#define CONFIG_SYS_LBC_MRTPR 0x20000000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +/* ------------------------------------------------------- + * DDR Setup + * ------------------------------------------------------- */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* + * Manually set up DDR parameters, + * as this board has not the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ + 0x00010000 |\ + CSCONFIG_ROW_BIT_13 |\ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((3< " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x00C00000 + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_MII +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_TIMESTAMP +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run nfsboot\\\" " \ + "to mount root filesystem over NFS;echo" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "run boot_cramfs" +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_JFFS2 + +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "0" +#define CONFIG_SYS_JFFS2_OFF "0" +#define CONFIG_MTD_NAND_ECC_JFFS2 + +/* mtdparts command line support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nor0=cu73x-0,nand0=cu73x-nand" +#define MTDPARTS_DEFAULT "mtdparts=cu73x-0:2M(kernel),5m(cramfs)," \ + "384k(u-boot),128k(env);" \ + "cu78d-nand:96m(jffs2),32m(jffs2)" + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ + "protect off " MK_STR(TEXT_BASE) " +${filesize}; " \ + "erase " MK_STR(TEXT_BASE) " +${filesize}; " \ + "cp.b ${loadaddr} " MK_STR(TEXT_BASE) " ${filesize}; " \ + "protect on " MK_STR(TEXT_BASE) " +${filesize}; " \ + "cmp.b ${loadaddr} " MK_STR(TEXT_BASE) " ${filesize}\0" \ + "console=ttyS0\0" \ + "fdtaddr=0x780000\0" \ + "kernel_addr=ff800000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "setbootargs=setenv bootargs " \ + "root=${rootdev} rw console=${console}," \ + "${baudrate} ${othbootargs}\0" \ + "setipargs=setenv bootargs root=${rootdev} rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off " \ + "console=${console},${baudrate} ${othbootargs}\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setipargs;" \ + "tftp ${loadaddr} ${bootfile};" \ + "tftp ${fdtaddr} ${fdtfile};" \ + "fdt addr ${fdtaddr};" \ + "bootm ${loadaddr} - ${fdtaddr}" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */