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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id q8sm18072840wiz.23.2015.10.27.08.08.10 (version=TLS1_1 cipher=AES128-SHA bits=128/128); Tue, 27 Oct 2015 08:08:10 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de Date: Tue, 27 Oct 2015 16:08:07 +0100 Message-Id: <3ca3e3eb8e9a9a3652cd2f96e869f3af16bec864.1445958486.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.5.0 Cc: Tom Rini , Joe Hershberger Subject: [U-Boot] [PATCH 1/3] net: zynq: Extend register description with offsets X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Extend comments with register offset to help with debuggging. Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- drivers/net/zynq_gem.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 72f1332c8008..d98c229f4330 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -108,28 +108,28 @@ /* Device registers */ struct zynq_gem_regs { - u32 nwctrl; /* Network Control reg */ - u32 nwcfg; /* Network Config reg */ - u32 nwsr; /* Network Status reg */ + u32 nwctrl; /* 0x0 - Network Control reg */ + u32 nwcfg; /* 0x4 - Network Config reg */ + u32 nwsr; /* 0x8 - Network Status reg */ u32 reserved1; - u32 dmacr; /* DMA Control reg */ - u32 txsr; /* TX Status reg */ - u32 rxqbase; /* RX Q Base address reg */ - u32 txqbase; /* TX Q Base address reg */ - u32 rxsr; /* RX Status reg */ + u32 dmacr; /* 0x10 - DMA Control reg */ + u32 txsr; /* 0x14 - TX Status reg */ + u32 rxqbase; /* 0x18 - RX Q Base address reg */ + u32 txqbase; /* 0x1c - TX Q Base address reg */ + u32 rxsr; /* 0x20 - RX Status reg */ u32 reserved2[2]; - u32 idr; /* Interrupt Disable reg */ + u32 idr; /* 0x2c - Interrupt Disable reg */ u32 reserved3; - u32 phymntnc; /* Phy Maintaince reg */ + u32 phymntnc; /* 0x34 - Phy Maintaince reg */ u32 reserved4[18]; - u32 hashl; /* Hash Low address reg */ - u32 hashh; /* Hash High address reg */ + u32 hashl; /* 0x80 - Hash Low address reg */ + u32 hashh; /* 0x84 - Hash High address reg */ #define LADDR_LOW 0 #define LADDR_HIGH 1 - u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ - u32 match[4]; /* Type ID1 Match reg */ + u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ + u32 match[4]; /* 0xa8 - Type ID1 Match reg */ u32 reserved6[18]; - u32 stat[44]; /* Octects transmitted Low reg - stat start */ + u32 stat[44]; /* 0x100 - Octects transmitted Low reg - stat start */ }; /* BD descriptors */