| Message ID | 20241024152448.102-14-paul.barker.ct@bp.renesas.com |
|---|---|
| State | New |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Add support for Ethernet interfaces on RZ/G2L | expand |
On 24/10/2024 16:24, Paul Barker wrote: > Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/[GV]2L SMARC > SoMs, as per RGMII specification. > > Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Acked-by: Linus Walleij <linus.walleij@linaro.org> > Link: https://lore.kernel.org/20240625200316.4282-5-paul.barker.ct@bp.renesas.com > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > [ upstream commit: 41c934da488d3a5a79148ead3b5c5eecac1b1d5d ] > > (cherry picked from commit 11cbf7bc3124f3d5267ea6aef8e4ba6d6b4f589e) Apologies Geert and Linus W, this and the following patch are for U-Boot. `git send-email` Cc'd you based on the Reviewed-by & Acked-by tags. You can safely ignore these :) I'll see if I can add some notes to the relevant U-Boot docs [1] [2] to use the `--no-signed-off-cc` argument to `git send-email` for such patches, so that myself and others hopefully don't make the same mistake in the future. [1]: https://docs.u-boot.org/en/latest/develop/process.html#resyncing-of-the-device-tree-subtree [2]: https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing Thanks,
On Thu, 24 Oct 2024 at 20:55, Paul Barker <paul.barker.ct@bp.renesas.com> wrote: > > Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/[GV]2L SMARC > SoMs, as per RGMII specification. > > Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Acked-by: Linus Walleij <linus.walleij@linaro.org> > Link: https://lore.kernel.org/20240625200316.4282-5-paul.barker.ct@bp.renesas.com > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > [ upstream commit: 41c934da488d3a5a79148ead3b5c5eecac1b1d5d ] > > (cherry picked from commit 11cbf7bc3124f3d5267ea6aef8e4ba6d6b4f589e) > --- > .../src/arm64/renesas/rzg2l-smarc-som.dtsi | 76 +++++++++++-------- > 1 file changed, 44 insertions(+), 32 deletions(-) > Acked-by: Sumit Garg <sumit.garg@linaro.org> -Sumit > diff --git a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi > index 4409c47239b9..2b5e037ea9fa 100644 > --- a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi > +++ b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi > @@ -180,41 +180,53 @@ > }; > > eth0_pins: eth0 { > - pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ > - <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ > - <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ > - <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ > - <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ > - <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ > - <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ > - <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ > - <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ > - <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ > - <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ > - <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ > - <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ > - <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ > - <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ > - <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ > + txc { > + pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */ > + output-enable; > + }; > + > + mux { > + pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ > + <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ > + <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ > + <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ > + <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ > + <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ > + <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ > + <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ > + <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ > + <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ > + <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ > + <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ > + <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ > + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ > + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ > + }; > }; > > eth1_pins: eth1 { > - pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */ > - <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ > - <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ > - <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */ > - <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ > - <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ > - <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ > - <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ > - <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ > - <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ > - <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ > - <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ > - <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ > - <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ > - <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ > - <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ > + txc { > + pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */ > + output-enable; > + }; > + > + mux { > + pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */ > + <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ > + <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ > + <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ > + <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ > + <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ > + <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ > + <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ > + <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ > + <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ > + <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ > + <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ > + <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ > + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ > + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ > + }; > }; > > gpio-sd0-pwr-en-hog { > -- > 2.43.0 >
diff --git a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi index 4409c47239b9..2b5e037ea9fa 100644 --- a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi +++ b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi @@ -180,41 +180,53 @@ }; eth0_pins: eth0 { - pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ - <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ - <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ - <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ - <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ - <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ - <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ - <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ - <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ - <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ - <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ - <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ - <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ - <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ - <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ + txc { + pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */ + output-enable; + }; + + mux { + pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ + <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ + }; }; eth1_pins: eth1 { - pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */ - <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ - <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ - <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */ - <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ - <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ - <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ - <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ - <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ - <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ - <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ - <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ - <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ - <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ - <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ + txc { + pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */ + output-enable; + }; + + mux { + pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */ + <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ + <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ + }; }; gpio-sd0-pwr-en-hog {