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Sun, 28 Apr 2024 07:24:21 -0700 (PDT) Received: from heesub-ubuntu.localdomain ([58.229.217.38]) by smtp.gmail.com with ESMTPSA id t3-20020a635343000000b005f077dce0f6sm17568744pgl.31.2024.04.28.07.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Apr 2024 07:24:21 -0700 (PDT) From: Heesub Shin To: u-boot@lists.denx.de Cc: Heesub Shin Subject: [PATCH 2/5] dts: stm32mp157c-odyssey: use internal clock for Tx Date: Sun, 28 Apr 2024 23:24:03 +0900 Message-Id: <20240428142406.28445-2-heesub@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240428142406.28445-1-heesub@gmail.com> References: <20240428142406.28445-1-heesub@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 28 Apr 2024 16:40:40 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In Odyssey board, we should use the internal clock from RCC as the transmit clock, instead of the external clock from ETH_CLK125 pad. This commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux selects ETH_CLK. Signed-off-by: Heesub Shin --- arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 17bcf56f74..53ba018197 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; + st,ext-phyclk; mdio0 { #address-cells = <1>;