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[2/5] dts: stm32mp157c-odyssey: use internal clock for Tx

Message ID 20240428142406.28445-2-heesub@gmail.com
State New
Delegated to: Patrice Chotard
Headers show
Series [1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK | expand

Commit Message

Heesub Shin April 28, 2024, 2:24 p.m. UTC 
In Odyssey board, we should use the internal clock from RCC as the
transmit clock, instead of the external clock from ETH_CLK125 pad. This
commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux
selects ETH_CLK.

Signed-off-by: Heesub Shin <heesub@gmail.com>
---
 arch/arm/dts/stm32mp157c-odyssey.dts | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts
index 17bcf56f74..53ba018197 100644
--- a/arch/arm/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/dts/stm32mp157c-odyssey.dts
@@ -75,6 +75,7 @@ 
 	phy-mode = "rgmii-id";
 	max-speed = <1000>;
 	phy-handle = <&phy0>;
+	st,ext-phyclk;
 
 	mdio0 {
 		#address-cells = <1>;