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Thu, 11 Apr 2024 15:37:43 -0700 (PDT) Received: from executor.attlocal.net ([2600:1700:5eb5:1ba0:dc1f:cff:fef9:435b]) by smtp.gmail.com with ESMTPSA id q11-20020a25f90b000000b00dcbbea79ffcsm482744ybe.42.2024.04.11.15.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 15:37:43 -0700 (PDT) From: Greg Malysa To: u-boot@lists.denx.de Cc: Arturs.Artamonovs@analog.com, Vasileios.Bimpikas@analog.com, Utsav.Agarwal@analog.com, Ian Roberts , Nathan Barrett-Morrison , Greg Malysa , Apurva Nandan , Dhruva Gole , Jagan Teki , Jan Kiszka , Tejas Bhumkar , Tom Rini Subject: [PATCH 06/11] spi: cadence-quadspi: unconditionally disable auto status register reads Date: Thu, 11 Apr 2024 18:36:50 -0400 Message-ID: <20240411223709.573-7-greg.malysa@timesys.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411223709.573-1-greg.malysa@timesys.com> References: <20240411223709.573-1-greg.malysa@timesys.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ian Roberts In addition to the given reason for the conditional disable of this feature for DTR: Theoretically, some flashes have their WIP bit in different bit positions or have a different bit polarity. spi-nor currently does not have an interface in place to dictate this information to this driver for proper configuration. The default of the controller hardware has this status register auto polling without expiration. This means that if there is any controller misconfiguration or communication failure, it will completely lock up the controller. Thus, unconditionally disable this feature for now. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi_apb.c | 46 ++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 176cff5338..d347cb8d47 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -853,19 +853,29 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); - if (priv->dtr) { - /* - * Some flashes like the cypress Semper flash expect a 4-byte - * dummy address with the Read SR command in DTR mode, but this - * controller does not support sending address with the Read SR - * command. So, disable write completion polling on the - * controller's side. spi-nor will take care of polling the - * status register. - */ - reg = readl(priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL); - reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; - writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL); - } + /* + * Some flashes like the cypress Semper flash expect a 4-byte + * dummy address with the Read SR command in DTR mode, but this + * controller does not support sending address with the Read SR + * command. So, disable write completion polling on the + * controller's side. spi-nor will take care of polling the + * status register. + * + * Theoretically, some flashes have their WIP bit in different + * bit positions or have a different bit polarity. spi-nor + * currently does not have an interface in place to dictate + * this information to this driver for proper configuration. + * + * The default of the controller hardware has this status register + * auto polling without expiration. This means that if there is any + * controller misconfiguration or communication failure, it will + * completely lock up the controller. + * + * Thus, unconditionally disable this feature for now. + */ + reg = readl(priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL); + reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; + writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL); reg = readl(priv->regbase + CQSPI_REG_SIZE); reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; @@ -970,16 +980,8 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; - /* - * Some flashes like the Cypress Semper flash expect a dummy 4-byte - * address (all 0s) with the read status register command in DTR mode. - * But this controller does not support sending dummy address bytes to - * the flash when it is polling the write completion register in DTR - * mode. So, we can not use direct mode when in DTR mode for writing - * data. - */ cadence_qspi_apb_enable_linear_mode(true); - if (!priv->dtr && priv->use_dac_mode && (to + len < priv->ahbsize)) { + if (priv->use_dac_mode && (to + len < priv->ahbsize)) { memcpy_toio(priv->ahbbase + to, buf, len); if (!cadence_qspi_wait_idle(priv->regbase)) return -EIO;