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Thu, 11 Apr 2024 15:37:46 -0700 (PDT) Received: from executor.attlocal.net ([2600:1700:5eb5:1ba0:dc1f:cff:fef9:435b]) by smtp.gmail.com with ESMTPSA id q11-20020a25f90b000000b00dcbbea79ffcsm482744ybe.42.2024.04.11.15.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 15:37:45 -0700 (PDT) From: Greg Malysa To: u-boot@lists.denx.de Cc: Arturs.Artamonovs@analog.com, Vasileios.Bimpikas@analog.com, Utsav.Agarwal@analog.com, Ian Roberts , Nathan Barrett-Morrison , Greg Malysa , Apurva Nandan , Ashok Reddy Soma , Igor Prusov , Jagan Teki , Johan Jonker , Neha Malcom Francis , Tejas Bhumkar , Tom Rini , Udit Kumar Subject: [PATCH 10/11] spi: cadence-quadspi: Add DT control of max Read Delay Capture value Date: Thu, 11 Apr 2024 18:36:54 -0400 Message-ID: <20240411223709.573-11-greg.malysa@timesys.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240411223709.573-1-greg.malysa@timesys.com> References: <20240411223709.573-1-greg.malysa@timesys.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ian Roberts On some SOCs (eg sc59x), attempting to use too high of a Read Delay Capture value can cause the controller DMA to lock up. Thus, add a device tree configuration property to allow controlling the max Read Delay Capture value. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- doc/device-tree-bindings/spi/spi-cadence.txt | 2 ++ drivers/spi/cadence_qspi.c | 9 ++++++++- drivers/spi/cadence_qspi.h | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt index 69e02c1c4b..9bd7ef8bed 100644 --- a/doc/device-tree-bindings/spi/spi-cadence.txt +++ b/doc/device-tree-bindings/spi/spi-cadence.txt @@ -29,3 +29,5 @@ connected flash properties select (n_ss_out). - cdns,tslch-ns : Delay in master reference clocks between setting n_ss_out low and first bit transfer +- cdns,max-read-delay : Max safe value to use for the read capture delay + during auto calibration. diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index a5e921cae7..3778a469d4 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -104,7 +104,7 @@ static int spi_calibration(struct udevice *bus, uint hz) /* use back the intended clock and find low range */ cadence_spi_write_speed(bus, hz); - for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { + for (i = 0; i < priv->max_read_delay; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -246,6 +246,7 @@ static int cadence_spi_probe(struct udevice *bus) priv->fifo_depth = plat->fifo_depth; priv->fifo_width = plat->fifo_width; priv->trigger_address = plat->trigger_address; + priv->max_read_delay = plat->max_read_delay; priv->read_delay = plat->read_delay; priv->ahbsize = plat->ahbsize; priv->max_hz = plat->max_hz; @@ -456,6 +457,10 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); + plat->max_read_delay = dev_read_u32_default(bus, + "cdns,max-read-delay", + CQSPI_READ_CAPTURE_MAX_DELAY); + /* All other parameters are embedded in the child node */ subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { @@ -484,6 +489,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus) */ plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay", -1); + if (plat->read_delay > plat->max_read_delay) + plat->read_delay = plat->max_read_delay; debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 9c15d3c6df..d7a02f0870 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -214,6 +214,7 @@ struct cadence_spi_plat { fdt_addr_t ahbsize; bool use_dac_mode; int read_delay; + int max_read_delay; /* Flash parameters */ u32 page_size; @@ -260,6 +261,7 @@ struct cadence_spi_priv { unsigned int previous_hz; u32 wr_delay; int read_delay; + int max_read_delay; struct reset_ctl_bulk *resets; u32 page_size;