From patchwork Tue Dec 26 06:17:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1880193 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Szl2K6mQVz20RL for ; Tue, 26 Dec 2023 17:18:17 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7639087809; Tue, 26 Dec 2023 07:18:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8534487823; Tue, 26 Dec 2023 07:17:59 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,RDNS_DYNAMIC, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 35772877D8 for ; Tue, 26 Dec 2023 07:17:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BQ6Hnxa084057 for ; Tue, 26 Dec 2023 14:17:49 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 26 Dec 2023 14:17:45 +0800 From: Leo Yu-Chi Liang To: CC: , , Subject: [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig Date: Tue, 26 Dec 2023 14:17:33 +0800 Message-ID: <20231226061736.482416-2-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226061736.482416-1-ycliang@andestech.com> References: <20231226061736.482416-1-ycliang@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BQ6Hnxa084057 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches. Provide the corresponding implementation to the options. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/cpu/andesv5/cpu.c | 25 ++++++++++++++++--------- board/AndesTech/ae350/ae350.c | 3 ++- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 63bc24cdfc..e764f6c5c0 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -32,18 +32,25 @@ void harts_early_init(void) if (CONFIG_IS_ENABLED(RISCV_MMODE)) { unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | - MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); + mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN; + + if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) + mcache_ctl_val |= MCACHE_CTL_IC_EN; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - /* - * Check mcache_ctl.DC_COHEN, we assume this platform does - * not support CM if the bit is hard-wired to 0. - */ - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { - /* Wait for DC_COHSTA bit to be set */ - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } } } } diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index 772c6bf1ee..bef9e3149e 100644 --- a/board/AndesTech/ae350/ae350.c +++ b/board/AndesTech/ae350/ae350.c @@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err) void spl_board_init() { /* enable v5l2 cache */ - enable_caches(); + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); } #endif