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[1/1] ARM: dts: chameleonv3: Update handoffs

Message ID 20231207153230.2471652-1-panikiel@google.com
State New
Delegated to: TIEN FONG CHEE
Headers show
Series [1/1] ARM: dts: chameleonv3: Update handoffs | expand

Commit Message

Paweł Anikiel Dec. 7, 2023, 3:32 p.m. UTC 
Update the chameleonv3 handoffs with the ones generated from the final
FPGA design.

Signed-off-by: Paweł Anikiel <panikiel@google.com>
---
 ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)
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Patch

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
index caaff604eb..37cd5d653d 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
@@ -13,9 +13,9 @@ 
 #define EMAC2_CLK_HZ 250000000
 #define EOSC1_CLK_HZ 33330000
 #define F2H_FREE_CLK_HZ 200000000
-#define H2F_USER0_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 250000000
 #define H2F_USER1_CLK_HZ 100000000
-#define L3_MAIN_FREE_CLK_HZ 200000000
+#define L3_MAIN_FREE_CLK_HZ 250000000
 #define SDMMC_CLK_HZ 200000000
 #define TPIU_CLK_HZ 100000000
 #define MAINPLLGRP_CNTR15CLK_CNT 900
@@ -24,7 +24,7 @@ 
 #define MAINPLLGRP_CNTR4CLK_CNT 900
 #define MAINPLLGRP_CNTR5CLK_CNT 900
 #define MAINPLLGRP_CNTR6CLK_CNT 9
-#define MAINPLLGRP_CNTR7CLK_CNT 9
+#define MAINPLLGRP_CNTR7CLK_CNT 7
 #define MAINPLLGRP_CNTR7CLK_SRC 0
 #define MAINPLLGRP_CNTR8CLK_CNT 19
 #define MAINPLLGRP_CNTR9CLK_CNT 900
@@ -68,7 +68,7 @@ 
 #define CLKMGR_TESTIOCTRL_PERICLKSEL 8
 #define ALTERAGRP_MPUCLK_MAINCNT 1
 #define ALTERAGRP_MPUCLK_PERICNT 900
-#define ALTERAGRP_NOCCLK_MAINCNT 9
+#define ALTERAGRP_NOCCLK_MAINCNT 7
 #define ALTERAGRP_NOCCLK_PERICNT 900
 #define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
 	(ALTERAGRP_MPUCLK_MAINCNT))
@@ -120,9 +120,9 @@ 
 #define CONFIG_IO_15_WK_PU_EN 1
 #define CONFIG_IO_16_INPUT_BUF_EN 0
 #define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PD_SLW_RT 0
 #define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_PU_SLW_RT 0
 #define CONFIG_IO_16_RTRIM 1
 #define CONFIG_IO_16_WK_PU_EN 0
 #define CONFIG_IO_17_INPUT_BUF_EN 1
@@ -169,9 +169,9 @@ 
 #define CONFIG_IO_5_WK_PU_EN 0
 #define CONFIG_IO_6_INPUT_BUF_EN 0
 #define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PD_SLW_RT 0
 #define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_PU_SLW_RT 0
 #define CONFIG_IO_6_RTRIM 1
 #define CONFIG_IO_6_WK_PU_EN 0
 #define CONFIG_IO_7_INPUT_BUF_EN 1
@@ -213,7 +213,7 @@ 
 #define PINMUX_DEDICATED_IO_9_SEL 8
 #define PINMUX_I2C0_USEFPGA_SEL 1
 #define PINMUX_I2C1_USEFPGA_SEL 0
-#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 1
 #define PINMUX_I2CEMAC1_USEFPGA_SEL 0
 #define PINMUX_I2CEMAC2_USEFPGA_SEL 0
 #define PINMUX_NAND_USEFPGA_SEL 0
@@ -283,10 +283,10 @@ 
 /* Bridge Configuration */
 #define F2H_AXI_SLAVE 1
 #define F2SDRAM0_AXI_SLAVE 1
-#define F2SDRAM1_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
 #define F2SDRAM2_AXI_SLAVE 1
 #define H2F_AXI_MASTER 1
-#define LWH2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 0
 
 /* Voltage Select for Config IO */
 #define CONFIG_IO_BANK_VSEL \