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Wed, 6 Dec 2023 03:51:41 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 6 Dec 2023 03:51:41 -0600 Received: from [127.0.1.1] (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3B69pQBZ039003; Wed, 6 Dec 2023 03:51:38 -0600 From: Manorit Chawdhry Date: Wed, 6 Dec 2023 15:21:25 +0530 Subject: [PATCH v6 3/8] binman: k3: Add k3-security.h and include it in k3-binman.dtsi MIME-Version: 1.0 Message-ID: <20231206-binman-firewalling-v6-3-e7fce13a6dc1@ti.com> References: <20231206-binman-firewalling-v6-0-e7fce13a6dc1@ti.com> In-Reply-To: <20231206-binman-firewalling-v6-0-e7fce13a6dc1@ti.com> To: Simon Glass , Alper Nebi Yasak , Neha Malcom Francis , Andrew Davis , Vignesh Raghavendra CC: , Udit Kumar , Praneeth Bajjuri , Kamlesh Gurudasani , Nishanth Menon , Thomas Richard , Gregory CLEMENT , Manorit Chawdhry X-Mailer: b4 0.13-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1701856286; l=3106; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=tevLs81SE/l8rDhXoaVLTh6y/iLCc/983RbSO+oA0AE=; b=Tph//xvtjaas2eMJyuRwrGoI9KOaPJGBq6kn4L/q1VqAzsMFPzcI0yiRfmZ9jfrn7bfoDZN7p 8qsKsCzDDvjBIeKMnXAJtY38wlQDnPLHvQbungEQu3tzaKd+MEnIYKr X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean For readability during configuring firewalls, adding k3-security.h file and including it in k3-binman.dtsi to be accessible across K3 SoCs Reviewed-by: Simon Glass Signed-off-by: Manorit Chawdhry --- arch/arm/dts/k3-binman.dtsi | 2 ++ arch/arm/dts/k3-security.h | 58 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index c7513e1a5dd7..b160192d18bf 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ */ +#include "k3-security.h" + / { binman: binman { multiple-images; diff --git a/arch/arm/dts/k3-security.h b/arch/arm/dts/k3-security.h new file mode 100644 index 000000000000..33609caa8fb5 --- /dev/null +++ b/arch/arm/dts/k3-security.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef DTS_ARM64_TI_K3_FIREWALL_H +#define DTS_ARM64_TI_K3_FIREWALL_H + +#define FWPRIVID_ALL 0xc3 +#define FWPRIVID_ARMV8 1 +#define FWPRIVID_SHIFT 16 + +#define FWCTRL_EN 0xA +#define FWCTRL_LOCK (1 << 4) +#define FWCTRL_BG (1 << 8) +#define FWCTRL_CACHE (1 << 9) + +#define FWPERM_SECURE_PRIV_WRITE (1 << 0) +#define FWPERM_SECURE_PRIV_READ (1 << 1) +#define FWPERM_SECURE_PRIV_CACHEABLE (1 << 2) +#define FWPERM_SECURE_PRIV_DEBUG (1 << 3) + +#define FWPERM_SECURE_PRIV_RWCD (FWPERM_SECURE_PRIV_READ | \ + FWPERM_SECURE_PRIV_WRITE | \ + FWPERM_SECURE_PRIV_CACHEABLE | \ + FWPERM_SECURE_PRIV_DEBUG) + +#define FWPERM_SECURE_USER_WRITE (1 << 4) +#define FWPERM_SECURE_USER_READ (1 << 5) +#define FWPERM_SECURE_USER_CACHEABLE (1 << 6) +#define FWPERM_SECURE_USER_DEBUG (1 << 7) + +#define FWPERM_SECURE_USER_RWCD (FWPERM_SECURE_USER_READ | \ + FWPERM_SECURE_USER_WRITE | \ + FWPERM_SECURE_USER_CACHEABLE | \ + FWPERM_SECURE_USER_DEBUG) + +#define FWPERM_NON_SECURE_PRIV_WRITE (1 << 8) +#define FWPERM_NON_SECURE_PRIV_READ (1 << 9) +#define FWPERM_NON_SECURE_PRIV_CACHEABLE (1 << 10) +#define FWPERM_NON_SECURE_PRIV_DEBUG (1 << 11) + +#define FWPERM_NON_SECURE_PRIV_RWCD (FWPERM_NON_SECURE_PRIV_READ | \ + FWPERM_NON_SECURE_PRIV_WRITE | \ + FWPERM_NON_SECURE_PRIV_CACHEABLE | \ + FWPERM_NON_SECURE_PRIV_DEBUG) + +#define FWPERM_NON_SECURE_USER_WRITE (1 << 12) +#define FWPERM_NON_SECURE_USER_READ (1 << 13) +#define FWPERM_NON_SECURE_USER_CACHEABLE (1 << 14) +#define FWPERM_NON_SECURE_USER_DEBUG (1 << 15) + +#define FWPERM_NON_SECURE_USER_RWCD (FWPERM_NON_SECURE_USER_READ | \ + FWPERM_NON_SECURE_USER_WRITE | \ + FWPERM_NON_SECURE_USER_CACHEABLE | \ + FWPERM_NON_SECURE_USER_DEBUG) + +#endif