diff mbox series

[v3,2/2] pci: xilinx: Enable MMIO region

Message ID 20231116165103.140968-3-mchitale@ventanamicro.com
State Accepted
Commit a62b01ded171415e0278bfc951a31895e63d166f
Delegated to: Michal Simek
Headers show
Series Xilinx PCI driver fixes | expand

Commit Message

Mayuresh Chitale Nov. 16, 2023, 4:51 p.m. UTC 
The host bridge MMIO region is disabled by default due to which MMIO
accesses cause an exception. Fix it by setting the bridge enable bit.
This change is ported from the linux pcie-xilinx driver.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
---
 drivers/pci/pcie_xilinx.c | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index fdc9b08c10..3db460b5f9 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -24,6 +24,8 @@  struct xilinx_pcie {
 /* Register definitions */
 #define XILINX_PCIE_REG_PSCR		0x144
 #define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
+#define XILINX_PCIE_REG_RPSC		0x148
+#define XILINX_PCIE_REG_RPSC_BEN	BIT(0)
 
 /**
  * pcie_xilinx_link_up() - Check whether the PCIe link is up
@@ -141,6 +143,7 @@  static int pcie_xilinx_of_to_plat(struct udevice *dev)
 	struct xilinx_pcie *pcie = dev_get_priv(dev);
 	fdt_addr_t addr;
 	fdt_size_t size;
+	u32 rpsc;
 
 	addr = dev_read_addr_size(dev, &size);
 	if (addr == FDT_ADDR_T_NONE)
@@ -150,6 +153,11 @@  static int pcie_xilinx_of_to_plat(struct udevice *dev)
 	if (IS_ERR(pcie->cfg_base))
 		return PTR_ERR(pcie->cfg_base);
 
+	/* Enable the Bridge enable bit */
+	rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+	rpsc |= XILINX_PCIE_REG_RPSC_BEN;
+	__raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+
 	return 0;
 }