From patchwork Fri Sep 22 10:39:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 1838187 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=ieFuTKyH; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RsTMF6k5nz1ynH for ; Fri, 22 Sep 2023 20:40:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B6FAC86BAA; Fri, 22 Sep 2023 12:40:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="ieFuTKyH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3A28F86BAE; Fri, 22 Sep 2023 12:40:32 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BE88C86B88 for ; Fri, 22 Sep 2023 12:40:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=n-francis@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38MAeRYu124056; Fri, 22 Sep 2023 05:40:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1695379227; bh=5W/uFspdVQThWNz/Tpa3JAkYjB9QIbbPVuTqR2HBh9Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ieFuTKyHjjg2FoGKvxuUZUkz8e9/LzmJsYmbLsKI+7QsfXYpj6M1YeEkKffFwGmPS oP8NnN2miSPMzrGpXJg68No63VK3Xv0GDULwMJibsDkjqGdxlVCItRkadT335xBfFO pBso0E66RkO0xz1YaW002GPQQM3UXLSQyDHYyFBA= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38MAeRdl013959 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 22 Sep 2023 05:40:27 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 22 Sep 2023 05:40:27 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 22 Sep 2023 05:40:27 -0500 Received: from a0497641-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38MAdtBw034669; Fri, 22 Sep 2023 05:40:21 -0500 From: Neha Malcom Francis To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v3 5/6] arm: dts: k3-j721e-r5: Clean up inclusion hierarchy Date: Fri, 22 Sep 2023 16:09:53 +0530 Message-ID: <20230922103954.3454891-6-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922103954.3454891-1-n-francis@ti.com> References: <20230922103954.3454891-1-n-francis@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Get rid of k3-j721e-r5-*-u-boot.dtsi as it is not necessary. Change the inclusion hierarchy to be as follows: k3-j721e-.dts--- - -->k3-j721e-r5-.dts - k3-j721e--u-boot.dtsi--- Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code although it could've been automatically done by U-Boot is to resolve some of the dependencies that R5 file requires. Also remove duplicate phandles while making this shift as well as remove firmware-loader as it serves no purpose without "phandlepart" property. Signed-off-by: Neha Malcom Francis --- .../k3-j721e-r5-common-proc-board-u-boot.dtsi | 29 ------------ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 38 +++------------ arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi | 31 ------------ arch/arm/dts/k3-j721e-r5-sk.dts | 47 ++++--------------- 4 files changed, 16 insertions(+), 129 deletions(-) delete mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi delete mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi deleted file mode 100644 index f9746d33ec..0000000000 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include "k3-j721e-common-proc-board-u-boot.dtsi" - -/ { - chosen { - firmware-loader = &fs_loader0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - fs_loader0: fs_loader@0 { - bootph-all; - compatible = "u-boot,fs-loader"; - }; -}; - -&tps659413a { - esm: esm { - compatible = "ti,tps659413-esm"; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 32f71e9b6a..7bb5ce775c 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -5,10 +5,10 @@ /dts-v1/; -#include "k3-j721e-som-p0.dtsi" +#include "k3-j721e-common-proc-board.dts" #include "k3-j721e-ddr-evm-lp4-4266.dtsi" #include "k3-j721e-ddr.dtsi" -#include "k3-j721e-binman.dtsi" +#include "k3-j721e-common-proc-board-u-boot.dtsi" #include / { @@ -198,27 +198,6 @@ >; }; - main_usbss0_pins_default: main_usbss0_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_mmc1_pins_default: main_mmc1_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ - >; - }; - main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ @@ -300,6 +279,11 @@ bootph-pre-ram; }; }; + + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; }; }; @@ -424,14 +408,6 @@ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>; assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; - serdes0_pcie_link: link@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>; - }; - serdes0_qsgmii_link: phy@1 { reg = <1>; cdns,num-lanes = <1>; diff --git a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi deleted file mode 100644 index 733d69cd00..0000000000 --- a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-j721e-sk-u-boot.dtsi" - -/ { - chosen { - firmware-loader = &fs_loader0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - remoteproc2 = &main_r5fss0_core0; - remoteproc3 = &main_r5fss0_core1; - }; - - fs_loader0: fs_loader@0 { - bootph-all; - compatible = "u-boot,fs-loader"; - }; -}; - -&tps659412 { - esm: esm { - compatible = "ti,tps659413-esm"; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index 6986292e37..1cc64d07f7 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -5,9 +5,10 @@ /dts-v1/; -#include "k3-j721e.dtsi" +#include "k3-j721e-sk.dts" #include "k3-j721e-ddr-sk-lp4-4266.dtsi" #include "k3-j721e-ddr.dtsi" +#include "k3-j721e-sk-u-boot.dtsi" / { model = "Texas Instruments J721E SK R5"; @@ -15,6 +16,8 @@ aliases { remoteproc0 = &sysctrler; remoteproc1 = &a72_0; + remoteproc2 = &main_r5fss0_core0; + remoteproc3 = &main_r5fss0_core1; }; chosen { @@ -279,52 +282,15 @@ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ >; }; - - mcu_i2c0_pins_default: mcu_i2c0_pins_default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */ - J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */ - >; - }; }; &main_pmx0 { - main_uart0_pins_default: main_uart0_pins_default { - bootph-pre-ram; - pinctrl-single,pins = < - J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ - J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_usbss0_pins_default: main_usbss0_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - main_usbss1_pins_default: main-usbss1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - main_mmc1_pins_default: main_mmc1_pins_default { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - >; - }; - main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ @@ -423,6 +389,11 @@ bootph-pre-ram; }; }; + + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; }; };