@@ -30,6 +30,68 @@
compatible = "qcom,gcc-reset-sdm845";
reg = <0x00100000 0x1f0000>;
#reset-cells = <1>;
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x01d84000 0x2500>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&reset GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 300000000>;
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sdm845-qmp-ufs-phy";
+ reg = <0x01d87000 0x18c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-names = "ref",
+ "ref_aux";
+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ ufs_mem_phy_lanes: phy@1d87400 {
+ reg = <0x01d87400 0x108>,
+ <0x01d87600 0x1e0>,
+ <0x01d87c00 0x1dc>,
+ <0x01d87800 0x108>,
+ <0x01d87a00 0x1e0>;
+ #phy-cells = <0>;
+ };
};
gpio_north: gpio_north@3900000 {
Add UFS HC and PHY nodes in Qualcomm SDM845 dtsi. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> --- arch/arm/dts/sdm845.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+)