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Mon, 14 Aug 2023 14:55:48 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1f3b:3924:6581:8508:2ecb:b5dd]) by smtp.gmail.com with ESMTPSA id n4-20020a170903110400b001bba373919bsm9872075plh.261.2023.08.14.14.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Aug 2023 14:55:48 -0700 (PDT) From: Bhupesh Sharma To: u-boot@lists.denx.de Cc: sjg@chromium.org, trini@konsulko.com, bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, marek.vasut+renesas@mailbox.org, sumit.garg@linaro.org, rfried.dev@gmail.com, patrice.chotard@foss.st.com, jbx6244@gmail.com, kever.yang@rock-chips.com, eugen.hristev@collabora.com Subject: [PATCH 09/17] ufs: Sync possible UFS Quirks with Linux UFS driver Date: Tue, 15 Aug 2023 03:24:49 +0530 Message-Id: <20230814215457.4075025-10-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230814215457.4075025-1-bhupesh.sharma@linaro.org> References: <20230814215457.4075025-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Sync u-boot UFS driver to add all possible UFS Quirks as supported by Linux UFS driver as well. Signed-off-by: Bhupesh Sharma --- drivers/ufs/ufs.h | 129 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 121 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index b3d2bd0368..cdc88919b4 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -712,14 +712,127 @@ struct ufs_hba { u32 version; u32 intr_mask; u32 quirks; -/* - * If UFS host controller is having issue in processing LCC (Line - * Control Command) coming from device then enable this quirk. - * When this quirk is enabled, host controller driver should disable - * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE - * attribute of device to 0). - */ -#define UFSHCD_QUIRK_BROKEN_LCC 0x1 + + /* Interrupt aggregation support is broken */ +#define UFSHCD_QUIRK_BROKEN_INTR_AGGR (1 << 0) + + /* + * delay before each dme command is required as the unipro + * layer has shown instabilities + */ +#define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS (1 << 1) + + /* + * If UFS host controller is having issue in processing LCC (Line + * Control Command) coming from device then enable this quirk. + * When this quirk is enabled, host controller driver should disable + * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE + * attribute of device to 0). + */ +#define UFSHCD_QUIRK_BROKEN_LCC (1 << 2) + + /* + * The attribute PA_RXHSUNTERMCAP specifies whether or not the + * inbound Link supports unterminated line in HS mode. Setting this + * attribute to 1 fixes moving to HS gear. + */ +#define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP (1 << 3) + + /* + * This quirk needs to be enabled if the host controller only allows + * accessing the peer dme attributes in AUTO mode (FAST AUTO or + * SLOW AUTO). + */ +#define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE (1 << 4) + + /* + * This quirk needs to be enabled if the host controller doesn't + * advertise the correct version in UFS_VER register. If this quirk + * is enabled, standard UFS host driver will call the vendor specific + * ops (get_ufs_hci_version) to get the correct version. + */ +#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION (1 << 5) + + /* + * Clear handling for transfer/task request list is just opposite. + */ +#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR (1 << 6) + + /* + * This quirk needs to be enabled if host controller doesn't allow + * that the interrupt aggregation timer and counter are reset by s/w. + */ +#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR (1 << 7) + + /* + * This quirks needs to be enabled if host controller cannot be + * enabled via HCE register. + */ +#define UFSHCI_QUIRK_BROKEN_HCE (1 << 8) + + /* + * This quirk needs to be enabled if the host controller regards + * resolution of the values of PRDTO and PRDTL in UTRD as byte. + */ +#define UFSHCD_QUIRK_PRDT_BYTE_GRAN (1 << 9) + + /* + * This quirk needs to be enabled if the host controller reports + * OCS FATAL ERROR with device error through sense data + */ +#define UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR (1 << 10) + + /* + * This quirk needs to be enabled if the host controller has + * auto-hibernate capability but it doesn't work. + */ +#define UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 (1 << 11) + + /* + * This quirk needs to disable manual flush for write booster + */ +#define UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL (1 << 12) + + /* + * This quirk needs to disable unipro timeout values + * before power mode change + */ +#define UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING (1 << 13) + + /* + * Align DMA SG entries on a 4 KiB boundary. + */ +#define UFSHCD_QUIRK_4KB_DMA_ALIGNMENT (1 << 14) + + /* + * This quirk needs to be enabled if the host controller does not + * support UIC command + */ +#define UFSHCD_QUIRK_BROKEN_UIC_CMD (1 << 15) + + /* + * This quirk needs to be enabled if the host controller cannot + * support physical host configuration. + */ +#define UFSHCD_QUIRK_SKIP_PH_CONFIGURATION (1 << 16) + + /* + * This quirk needs to be enabled if the host controller has + * 64-bit addressing supported capability but it doesn't work. + */ +#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS (1 << 17) + + /* + * This quirk needs to be enabled if the host controller has + * auto-hibernate capability but it's FASTAUTO only. + */ +#define UFSHCD_QUIRK_HIBERN_FASTAUTO (1 << 18) + + /* + * This quirk needs to be enabled if the host controller needs + * to reinit the device after switching to maximum gear. + */ +#define UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH (1 << 19) /* Virtual memory reference */ struct utp_transfer_cmd_desc *ucdl;