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Reviewed-by: Neha Malcom Francis Signed-off-by: Nishanth Menon --- Changes since V1 * Picked up reviewed-by V1: https://lore.kernel.org/all/20230727080027.2817701-3-nm@ti.com/ doc/board/ti/am62x_sk.rst | 68 +- doc/board/ti/img/boot_diagram_k3_current.svg | 1925 ++++++++++++++++++ doc/board/ti/j7200_evm.rst | 85 +- 3 files changed, 1927 insertions(+), 151 deletions(-) create mode 100644 doc/board/ti/img/boot_diagram_k3_current.svg diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index ba017a2b489e..f511b5935c16 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -42,73 +42,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. code-block:: text - - +------------------------------------------------------------------------+ - | TIFS | Main R5 | A53 | - +------------------------------------------------------------------------+ - | +--------+ | | | - | | Reset | | | | - | +--------+ | | | - | : | | | - | +--------+ | +-----------+ | | - | | *ROM* |----------|-->| Reset rls | | | - | +--------+ | +-----------+ | | - | | | | : | | - | | ROM | | : | | - | |services| | : | | - | | | | +-------------+ | | - | | | | | *R5 ROM* | | | - | | | | +-------------+ | | - | | |<---------|---|Load and auth| | | - | | | | | tiboot3.bin | | | - | +--------+ | +-------------+ | | - | | |<---------|---| Load sysfw | | | - | | | | | part to TIFS| | | - | | | | | core | | | - | | | | +-------------+ | | - | | | | : | | - | | | | : | | - | | | | : | | - | | | | +-------------+ | | - | | | | | *R5 SPL* | | | - | | | | +-------------+ | | - | | | | | DDR | | | - | | | | | config | | | - | | | | +-------------+ | | - | | | | | Load | | | - | | | | | tispl.bin | | | - | | | | +-------------+ | | - | | | | | Load R5 | | | - | | | | | firmware | | | - | | | | +-------------+ | | - | | |<---------|---| Start A53 | | | - | | | | | and jump to | | | - | | | | | DM fw image | | | - | | | | +-------------+ | | - | | | | | +-----------+ | - | | |----------|-----------------------|---->| Reset rls | | - | | | | | +-----------+ | - | | TIFS | | | : | - | |Services| | | +-------------+ | - | | |<---------|-----------------------|---->|*TF-A/OP-TEE*| | - | | | | | +-------------+ | - | | | | | : | - | | | | | +-----------+ | - | | |<---------|-----------------------|---->| *A53 SPL* | | - | | | | | +-----------+ | - | | | | | | Load | | - | | | | | | u-boot.img| | - | | | | | +-----------+ | - | | | | | : | - | | | | | +-----------+ | - | | |<---------|-----------------------|---->| *U-Boot* | | - | | | | | +-----------+ | - | | | | | | prompt | | - | | |----------|-----------------------|-----+-----------+-----| - | +--------+ | | | - | | | | - +------------------------------------------------------------------------+ +.. image:: img/boot_diagram_k3_current.svg - Here TIFS acts as master and provides all the critical services. R5/A53 requests TIFS to get these services done as shown in the above diagram. diff --git a/doc/board/ti/img/boot_diagram_k3_current.svg b/doc/board/ti/img/boot_diagram_k3_current.svg new file mode 100644 index 000000000000..995afd890e12 --- /dev/null +++ b/doc/board/ti/img/boot_diagram_k3_current.svg @@ -0,0 +1,1925 @@ + + + + + + + + + + + + + Cortex-R + + + + Cortex-R + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + Cortex-R SPL + + + + Cortex-R SPL + + + + + + + + + Load and auth tiboot3.bin + + + + Load and auth t... + + + + + + + + + Load system +config data + + + + Load system... + + + + + + + + + DDR Config + + + + DDR Config + + + + + + + + + Load tispl.bin + + + + Load tispl.bin + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + Start DM + + + + Start DM + + + + + + + + + + Device Mgr + + + + Device Mgr + + + + + + + + + + Start Cortex-A + + + + Start Cort... + + + + + + + + + + + + + + + + + + + + + + + + Cortex-A + + + + Cortex-A + + + + + + + + + + + + + Cortex-R/M +C6x/C7x + + + + Cortex-R/M... + + + + + + + + + + Aux f/w + + + + Aux f/w + + + + + + + + + + TIFS/DMSC + + + + TIFS/DMSC + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + TIFS + + + + TIFS + + + + + + + + + + Security Enclave Boot Processor + + + + Security Enclave Boot... + + + + + + + + + + Boot Loader +Processor + + + + Boot Loader... + + + + + + + + + + Main CPU + + + + Main CPU + + + + + + + + + + Auxiliary +Processor + + + + Auxiliary... + + + + + + + + + + H/w Seq: Reset rls + + + + H/w Seq: Reset rls + + + + + + + + + + Auth tiboot3.bin + + + + Auth tiboo... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + + Load system config data + + + + Load syste... + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + Load DM f/w + + + + Load DM f/w + + + + + + + + + + branch + + + + branch + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + TF-A + + + + TF-A + + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + + Cortex-A SPL + + + + Cortex-A SPL + + + + + + + + + + U-Boot + + + + U-Boot + + + + + + + + + Load u-boot.img + + + + Load u-boot.img + + + + + + + + + Load Aux core f/w +(optional) + + + + Load Aux core f/w... + + + + + + + + + Start Aux core +(optional) + + + + Start Aux core... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index f81e3f43b7d7..fea01b55e2a1 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -30,90 +30,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. code-block:: text - - +------------------------------------------------------------------------+-----------------------+ - | DMSC | MCU R5 | A72 | MAIN R5/C7x | - +------------------------------------------------------------------------+-----------------------+ - | +--------+ | | | | - | | Reset | | | | | - | +--------+ | | | | - | : | | | | - | +--------+ | +-----------+ | | | - | | *ROM* |----------|-->| Reset rls | | | | - | +--------+ | +-----------+ | | | - | | | | : | | | - | | ROM | | : | | | - | |services| | : | | | - | | | | +-------------+ | | | - | | | | | *R5 ROM* | | | | - | | | | +-------------+ | | | - | | |<---------|---|Load and auth| | | | - | | | | | tiboot3.bin | | | | - | | Start | | +-------------+ | | | - | | TIFS |<---------|---| Start | | | | - | | | | | TIFS | | | | - | +--------+ | +-------------+ | | | - | : | | | | | | - | +---------+ | | Load | | | | - | | *TIFS* | | | system | | | | - | +---------+ | | Config data | | | | - | | |<--------|---| | | | | - | | | | +-------------+ | | | - | | | | : | | | - | | | | : | | | - | | | | : | | | - | | | | +-------------+ | | | - | | | | | *R5 SPL* | | | | - | | | | +-------------+ | | | - | | | | | DDR | | | | - | | | | | config | | | | - | | | | +-------------+ | | | - | | | | | Load | | | | - | | | | | tispl.bin | | | | - | | | | +-------------+ | | | - | | | | | Load R5 | | | | - | | | | | firmware | | | | - | | | | +-------------+ | | | - | | |<--------|---| Start A72 | | | | - | | | | | and jump to | | | | - | | | | | DM fw image | | | | - | | | | +-------------+ | | | - | | | | | +-----------+ | | - | | |---------|-----------------------|---->| Reset rls | | | - | | | | | +-----------+ | | - | | TIFS | | | : | | - | |Services | | | +-------------+ | | - | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | - | | | | | +-------------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *A72 SPL* | | | - | | | | | +-----------+ | | - | | | | | | Load | | | - | | | | | | u-boot.img| | | - | | | | | +-----------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *U-Boot* | | | - | | | | | +-----------+ | | - | | | | | | prompt | | | - | | | | | +-----------+ | | - | | | | | | Load R5 | | | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | - | | | | | | Load C7 | | +-----------+ | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | - | | | | | | +-----------+ | - | | | | | | | - | +---------+ | | | | - | | | | | - +------------------------------------------------------------------------+-----------------------+ +.. image:: img/boot_diagram_k3_current.svg - Here DMSC acts as master and provides all the critical services. R5/A72 requests DMSC to get these services done as shown in the above diagram.