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[1/6] dma: ti: Update J21E PSIL endpoint information for MAIN CPSW0

Message ID 20230708104523.228257-2-s-vadapalli@ti.com
State Changes Requested
Delegated to: Tom Rini
Headers show
Series Add SGMII support for MAIN CPSW on TI's J7200 SoC | expand

Commit Message

Siddharth Vadapalli July 8, 2023, 10:45 a.m. UTC 
From: Suman Anna <s-anna@ti.com>

The PSIL endpoint data for J721E currently covers only the MCU domain
CPSW0 instance. Add the data for the MAIN domain CPSW0 as well to allow
the MAIN domain Ethernet ports to be usable on any platform using J721E
SoC.

Additionally, since J721E's PSIL endpoint data is applicable to J7200
SoC as well, the MAIN CPSW0 instance on J7200 will also be usable now.

Signed-off-by: Suman Anna <s-anna@ti.com>
[s-vadapalli@ti.com: Update commit message indicating support for J7200]
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/dma/ti/k3-psil-j721e.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)
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Patch

diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c
index 105ffd946f..8e57e860f2 100644
--- a/drivers/dma/ti/k3-psil-j721e.c
+++ b/drivers/dma/ti/k3-psil-j721e.c
@@ -1,6 +1,6 @@ 
 // SPDX-License-Identifier: GPL-2.0
 /*
- *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *  Copyright (C) 2019-2023 Texas Instruments Incorporated - https://www.ti.com
  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  */
 
@@ -21,13 +21,15 @@ 
 
 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
 static struct psil_ep j721e_src_ep_map[] = {
-	/* CPSW0 */
+	/* MCU_CPSW0 */
 	PSIL_ETHERNET(0x7000),
+	/* MAIN_CPSW0 */
+	PSIL_ETHERNET(0x4a00),
 };
 
 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
 static struct psil_ep j721e_dst_ep_map[] = {
-	/* CPSW0 */
+	/* MCU_CPSW0 */
 	PSIL_ETHERNET(0xf000),
 	PSIL_ETHERNET(0xf001),
 	PSIL_ETHERNET(0xf002),
@@ -36,6 +38,15 @@  static struct psil_ep j721e_dst_ep_map[] = {
 	PSIL_ETHERNET(0xf005),
 	PSIL_ETHERNET(0xf006),
 	PSIL_ETHERNET(0xf007),
+	/* MAIN_CPSW0 */
+	PSIL_ETHERNET(0xca00),
+	PSIL_ETHERNET(0xca01),
+	PSIL_ETHERNET(0xca02),
+	PSIL_ETHERNET(0xca03),
+	PSIL_ETHERNET(0xca04),
+	PSIL_ETHERNET(0xca05),
+	PSIL_ETHERNET(0xca06),
+	PSIL_ETHERNET(0xca07),
 };
 
 struct psil_ep_map j721e_ep_map = {