From patchwork Wed Jun 21 15:11:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1797964 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QmRnP4glSz20Wk for ; Thu, 22 Jun 2023 01:12:25 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6423886374; Wed, 21 Jun 2023 17:12:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 05AF7846E6; Wed, 21 Jun 2023 17:12:16 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 412E486374 for ; Wed, 21 Jun 2023 17:12:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinylab.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bmeng@tinylab.org X-QQ-mid: bizesmtp66t1687360315thziwe1n Received: from pek-vx-bsp2.wrs.com ( [60.247.85.88]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 21 Jun 2023 23:11:54 +0800 (CST) X-QQ-SSF: 01200000000000E0G000000A0000000 X-QQ-FEAT: 7jw2iSiCazrLZcb4knrbH/UfXFT09JPY2tSJ3WmhQswfyJGQxP+GyMeGWSfxg ftZOHETGrzCcMnWA/U3LDr3lFm0RULuHdRuvwR2W/+t7qM1MDJb4gtYUmMpZd69yhhNuayK UEnjFOMbg4D7DLSDLwXxk3Tc6ARujSo5E/iUKWtzY74jIKkbYuraRoB0ve7wufaHeozbIic SEr6znlP0EP+8OJKyfV0vui7p3dtNHyjIQc/sKy4iQ4fHqYAEK9rJMXLM3iKIksCw+NVTem jhaGVfik7eRz70zBfNXM9Bo/S5tCOSx2A34jcrWPQaEhxLCF7+cmzyLfSC5OV1JfbLmz/hI vOrrGIYd1G1iqsBzqA1x1RmcA/8GgJqu5V6Nk4EFgypmxYxnccgwucE/8miRQ== X-QQ-GoodBg: 0 X-BIZMAIL-ID: 8115259883337870991 From: Bin Meng To: u-boot@lists.denx.de Cc: Anup Patel , Atish Patra , Bin Meng , Palmer Dabbelt , Paul Walmsley , Rick Chen Subject: [PATCH v2 1/3] riscv: timer: Update the sifive clint timer driver to support aclint Date: Wed, 21 Jun 2023 23:11:44 +0800 Message-Id: <20230621151147.1523273-2-bmeng@tinylab.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230621151147.1523273-1-bmeng@tinylab.org> References: <20230621151147.1523273-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvrgz:qybglogicsvrgz7a-0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: - drop ae350.h changes drivers/timer/sifive_clint_timer.c | 16 +++++++++++----- include/configs/qemu-riscv.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/starfive-visionfive2.h | 1 + 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index 939b99d937..be45f17ddf 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -12,12 +12,16 @@ #include #include +#define CLINT_MTIME_OFFSET 0xbff8 +#define ACLINT_MTIME_OFFSET 0 + /* mtime register */ -#define MTIME_REG(base) ((ulong)(base) + 0xbff8) +#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) static u64 notrace sifive_clint_get_count(struct udevice *dev) { - return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), + dev_get_driver_data(dev))); } #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) @@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void) */ u64 notrace timer_early_get_count(void) { - return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); } #endif @@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev) } static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0" }, - { .compatible = "sifive,clint0" }, + { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, + { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, { } }; diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 20135f569e..f6d326bda0 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -11,8 +11,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index de3a0dcdd5..f208f5e20d 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -14,8 +14,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 93dcc22d36..4ee02b8420 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -9,6 +9,7 @@ #define _STARFIVE_VISIONFIVE2_H #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 4000000 #define RISCV_SMODE_TIMER_FREQ 4000000