From patchwork Wed Jun 21 14:06:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1797921 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Ii5Cpxke; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QmQLG3zH8z20Xg for ; Thu, 22 Jun 2023 00:07:16 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 91E7486351; Wed, 21 Jun 2023 16:07:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ii5Cpxke"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 83EDD8636F; Wed, 21 Jun 2023 16:07:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6BF838622C for ; Wed, 21 Jun 2023 16:07:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687356421; x=1718892421; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=QDszMuJiVVJsRHw7wkvehQp8bjFBmTwA6LjRZ85/Cpc=; b=Ii5Cpxke4JEUg5ixxCVRtCum8IkfZ3yEVwRfOrvERjbZiear9CaifR/z 9oeBcmE2HAb1piK3t5sKYoedKNxTlWAT9A6vBFIOZ5yh8q+02piWrHVsr zKq3gNRZrsNbm9lEfN7atTfIj0L9ACas/ov1eZc5cbVGyqJ77xRz+pv6K L94DXqd6Pe5mRwFhys+VUAF8SmyDsT8Twpq68cDNmrCFG05WHqXAgNfxJ 0OFjjVIYW6Yca6SoBm50IDnPHGv9H9KHlWqAMMLmrCi8FO21WexqLq30c C5yGOZ9yoIuqqFtKcZrLn0Dj4cKnICU15wSxEHtwAGv9Cd/qOYpPZKPHI g==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="426135274" X-IronPort-AV: E=Sophos;i="6.00,260,1681196400"; d="scan'208";a="426135274" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 07:06:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="804392261" X-IronPort-AV: E=Sophos;i="6.00,260,1681196400"; d="scan'208";a="804392261" Received: from pglmail07.png.intel.com ([10.221.193.207]) by FMSMGA003.fm.intel.com with ESMTP; 21 Jun 2023 07:06:53 -0700 Received: from localhost (pgli0121.png.intel.com [10.221.240.84]) by pglmail07.png.intel.com (Postfix) with ESMTP id EEBC1482D; Wed, 21 Jun 2023 22:06:52 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id B4E903E08; Wed, 21 Jun 2023 22:06:52 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Marek , Simon , Tien Fong , Kok Kiang , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ying-Chun Liu , Marc Zyngier , Kah Jing Lee Subject: [PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL Date: Wed, 21 Jun 2023 22:06:51 +0800 Message-Id: <20230621140651.12756-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Kah Jing Lee Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL. Signed-off-by: Kah Jing Lee --- arch/arm/cpu/armv8/cache_v8.c | 20 +++++++++++--------- common/spl/Kconfig | 7 +++++++ 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index cb1131a048..7f25d3a6ce 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -534,29 +534,31 @@ inline void flush_dcache_all(void) #endif } -#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS -/* - * Invalidates range in all levels of D-cache/unified cache - */ +#if CONFIG_IS_ENABLED(SYS_DISABLE_DCACHE_OPS) || \ + CONFIG_IS_ENABLED(SPL_SYS_DISABLE_DCACHE_OPS) && \ + CONFIG_IS_ENABLED(SPL_BUILD) void invalidate_dcache_range(unsigned long start, unsigned long stop) { - __asm_invalidate_dcache_range(start, stop); } -/* - * Flush range(clean & invalidate) from all levels of D-cache/unified cache - */ void flush_dcache_range(unsigned long start, unsigned long stop) { - __asm_flush_dcache_range(start, stop); } #else +/* + * Invalidates range in all levels of D-cache/unified cache + */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { + __asm_invalidate_dcache_range(start, stop); } +/* + * Flush range(clean & invalidate) from all levels of D-cache/unified cache + */ void flush_dcache_range(unsigned long start, unsigned long stop) { + __asm_flush_dcache_range(start, stop); } #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */ diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2c042ad306..7e458503df 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -19,6 +19,13 @@ config SPL menu "SPL configuration options" depends on SPL +config SPL_SYS_DISABLE_DCACHE_OPS + bool "Do not enable dcache operation in SPL" + depends on SPL + help + Do not enable data cache operation in SPL. This will turn off the + Dcache support and have the empty dcache declaration. + config SPL_FRAMEWORK bool "Support SPL based upon the common SPL framework" default y