From patchwork Thu Jun 1 10:00:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 1788926 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=r7+2UE5m; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=J5YhhS13; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QX1r53CPzz20QB for ; Thu, 1 Jun 2023 20:01:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1398C862DD; Thu, 1 Jun 2023 12:00:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1685613658; bh=CHM55tD60BH+54USUqCeLs3WUl+mg20Fb/yRAR+jG5c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=r7+2UE5mKB/DK5w6vSrTFqBB7xnPf3ojbf8VGJSqG5LFbDy7FU1fUNXJxVPf/X6p8 6O2zvPQYuDfebdnjSuNjCMbXtDusF2qMhbhaOPe/SsJtZwSDYWMKSA6huclK39YL2o 6CGRNAiaeleRDpud/W9QenSNlkwzDJj8sRjGzE/G+GBBxXpa73+xGXYnLTE+b10FUb ej4r740kPdX9jzx2TZTlcSBDNx2+Qf9LSNWDgFI7r/QbtznczjBXW31o8ZzRyIr487 MzJAMM94IRvepkGP+tggpW3SCCwtfeLMY1KyqXJ1IJYFuSfVi4E0mZxTXNQlayq/hH WjN648qE2lPmA== Received: from localhost.localdomain (85-222-111-42.dynamic.chello.pl [85.222.111.42]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: lukma@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 132F6862DC; Thu, 1 Jun 2023 12:00:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1685613634; bh=CHM55tD60BH+54USUqCeLs3WUl+mg20Fb/yRAR+jG5c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J5YhhS13Z8VMF8RqEm1hzMuA1bb+UN+l4SG9tk5wtkU4kUvGAVOiEHFnWcY8Sgglc MNZsFS9tclko6lhcLrl6YjyFALUUzO7hlRoQYrOFR+42Nl7gIpezjI9H78RKb/Sexc JrN5ao8aplLyPceEZZmH9izslhD7VuPvSdgxlFU584g2WjfwnMNpCYK+OJ4RVJsXsL j88l/lszwXX30JdPs0mrXN3xnPA4FvM68hPcZnRnbSfmuX9yX4nDwtNN8U9vDEDfqZ HYSKMF7aBObuMyXaYtO1R7cJec4Tg37Lj+ba/OkX8deIGjiEQ5r1dbueJX1BKznLlN H1kKLXU4sl1BA== From: Lukasz Majewski To: u-boot@lists.denx.de, Tom Rini Cc: Anatolij Gustschin , Lukasz Majewski , Ramon Fried , Joe Hershberger , Marek Vasut , Michal Simek Subject: [PATCH v1 6/6] net: mv88e61xx: Reset switch PHYs when bootstrapped to !NO_CPU Date: Thu, 1 Jun 2023 12:00:05 +0200 Message-Id: <20230601100005.2216345-7-lukma@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230601100005.2216345-1-lukma@denx.de> References: <20230601100005.2216345-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some devices, when configured in bootstrap to 'no cpu' mode require PHY manual reset to get them operational and responding to reading their ID registers. Without this step - the PHYLIB probing will fail. In more details - the bootstrap configuration from switch must be read. The value of CONFIG Data1 (0x71) of Scratch and Misc register is read to check if 'no_cpu' and 'addr4' bits were set. Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 63 +++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 69a87bead469..cf8f5e833e82 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -194,6 +194,17 @@ struct mv88e61xx_phy_priv { u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */ u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */ u8 direct_access; /* Access switch device directly */ + /* + * Bootstrap configuration: + * + * If addr4 = 1 device is accessible from 0x10 address on MDIO bus. + */ + u8 addr4; + /* + * If no_cpu = 1 switch is automatically setup, otherwise PHY reset is + * required from CPU for normal operation. + */ + u8 no_cpu; }; static inline int smi_cmd(int cmd, int addr, int reg) @@ -1218,6 +1229,33 @@ U_BOOT_PHY_DRIVER(mv88e6071) = { .shutdown = &genphy_shutdown, }; +static int mv88e61xx_read_bootstrap(struct phy_device *phydev) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + struct mii_dev *mdio_bus = priv->mdio_bus; + int val; + + /* mv88e6020 - ID = 0x0200 (REG 3 on non PHY port) */ + if (priv->id == PORT_SWITCH_ID_6020) { + /* Prepare to read scratch and misc register */ + mdio_bus->write(mdio_bus, priv->global2, 0, + 0x1a /*MV_SCRATCH_MISC*/, + (0x71 /*MV_CONFIG_DATA1*/ << 8)); + + val = mdio_bus->read(mdio_bus, priv->global2, 0, + 0x1a /*MV_SCRATCH_MISC*/); + + if (val & (1 << 0)) + priv->no_cpu = 1; + if (val & (1 << 4)) + priv->addr4 = 1; + debug("mv88e6020: no_cpu=%d addr4=%d\n", priv->no_cpu, + priv->addr4); + } + + return 0; +} + /* * Overload weak get_phy_id definition since we need non-standard functions * to read PHY registers @@ -1257,13 +1295,34 @@ int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) if (val < 0) return val; - val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1); + mv88e61xx_read_bootstrap(&temp_phy); + + /* + * When switch is configured to work with CPU (i.e. NO_CPU == 0), PHYs + * require reset (to at least single one) to have its registers + * accessible. + */ + if (!temp_priv.no_cpu && temp_priv.id == PORT_SWITCH_ID_6020) { + /* Reset PHY */ + val = mv88e61xx_phy_read_indirect(&temp_mii, temp_phy.addr, + devad, MII_BMCR); + if (val & BMCR_PDOWN) + val &= ~BMCR_PDOWN; + + mv88e61xx_phy_write_indirect(&temp_mii, temp_phy.addr, devad, + MII_BMCR, val); + } + + /* Read PHY_ID */ + val = mv88e61xx_phy_read_indirect(&temp_mii, temp_phy.addr, devad, + MII_PHYSID1); if (val < 0) return -EIO; *phy_id = val << 16; - val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2); + val = mv88e61xx_phy_read_indirect(&temp_mii, temp_phy.addr, devad, + MII_PHYSID2); if (val < 0) return -EIO;