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[v3,17/17] x86: samus: Adjust TPL start and pre-reloc memory size

Message ID 20230504225101.2366414-18-sjg@chromium.org
State Accepted
Commit b982f89c583c6c03f4d1f94d29991ccf691a0f7c
Delegated to: Bin Meng
Headers show
Series x86: Various fixes for chromebooks | expand

Commit Message

Simon Glass May 4, 2023, 10:51 p.m. UTC 
Move the TPL up a little to make room for the refcode binary blob. Also
increase the pre-relocation memory to make space for recent additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

(no changes since v2)

Changes in v2:
- Drop patch "x86: Add on to existing MTRRs in SPL"
- Add various patches to resolve problems with chromebook_link64

 configs/chromebook_samus_tpl_defconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 337768b45fd..4cfaf4bc5c7 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -1,6 +1,6 @@ 
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0xffed0000
-CONFIG_SYS_MALLOC_F_LEN=0x1a00
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x3F8000
@@ -8,7 +8,7 @@  CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
 CONFIG_SPL_TEXT_BASE=0xffe70000
-CONFIG_TPL_TEXT_BASE=0xfffd8000
+CONFIG_TPL_TEXT_BASE=0xfffd8100
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y