From patchwork Sun Apr 23 18:11:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sin.hui.kho@intel.com X-Patchwork-Id: 1772486 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=brfzZRgV; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q4GZ91pQQz23s0 for ; Mon, 24 Apr 2023 04:12:17 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3D84C8609B; Sun, 23 Apr 2023 20:11:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="brfzZRgV"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 38F2285D95; Sun, 23 Apr 2023 20:11:45 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 55EAF8575B for ; Sun, 23 Apr 2023 20:11:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sin.hui.kho@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682273501; x=1713809501; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/Zc9QamfkMdczcLiK27/PnnZv5BIcCFsqSH47TDEfF8=; b=brfzZRgVZCv1UnknU9/u2FxsNeDdgcslO2cp8c8NjeVvPOhz3rHm501L lMgme+VTprcESyLG1L+UEUppzeJDKGi7tQaJn6ZUmyilgpZRjPSzg+NXA rpsdUjT6mM3+riZrqQy9LCjzZquVenqn/pPWZr56id6zfc8dgpms8Dl+r VpymVAL6LipMZ8jzwv1L9hOMrccPHvf22ETPtI0azySgdx2QE9S+WeZxe 3LJ5TAJCiamOn967r+TeCpPJjIgbG+SnQl4I+/ZXZhrwybuIZGymkDX45 NC/2Wilx2uQupj8K8XX6KnoALHcKv6KSt8Kl/rrPQhe4tEh8mycApc4kr w==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="374248728" X-IronPort-AV: E=Sophos;i="5.99,220,1677571200"; d="scan'208";a="374248728" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2023 11:11:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="695507804" X-IronPort-AV: E=Sophos;i="5.99,220,1677571200"; d="scan'208";a="695507804" Received: from pglc00257.png.intel.com ([10.221.233.180]) by fmsmga007.fm.intel.com with ESMTP; 23 Apr 2023 11:11:38 -0700 From: sin.hui.kho@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Tien Fong Chee , Sin Hui Kho , Simon Glass , Stefan Roese , Dinesh Maniyam , Jit Loon Lim , Teik Heng , Kok Kiang Subject: [PATCH v1 2/5] arm: socfpga: agilex7: Add boot scratch register used for DDR driver Date: Mon, 24 Apr 2023 02:11:21 +0800 Message-Id: <20230423181124.28077-3-sin.hui.kho@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230423181124.28077-1-sin.hui.kho@intel.com> References: <20230423181124.28077-1-sin.hui.kho@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Sin Hui Kho Add boot scratch register 8 in system manager used for AGILEX7 DDR driver. Signed-off-by: Sin Hui Kho --- .../include/mach/system_manager_soc64.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fe..fe85c0742d 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019-2021 Intel Corporation + * Copyright (C) 2019-2023 Intel Corporation */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -102,6 +102,23 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DDR DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[29] reserved for FSBL to check OCRAM DBE is triggered (set by SDM to "1") + * + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_SHIFT 27 #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC