diff mbox series

riscv: Correct a comment in io.h

Message ID 20230403033732.2812219-1-bmeng@tinylab.org
State Accepted
Commit 16f53be076512e888a572297df10484df7a32849
Delegated to: Andes
Headers show
Series riscv: Correct a comment in io.h | expand

Commit Message

Bin Meng April 3, 2023, 3:37 a.m. UTC
Replace NDS32 with RISC-V in the comments.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
---

 arch/riscv/include/asm/io.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Rick Chen April 6, 2023, 1:33 a.m. UTC | #1
> From: Bin Meng <bmeng@tinylab.org>
> Sent: Monday, April 03, 2023 11:38 AM
> To: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>
> Cc: u-boot@lists.denx.de
> Subject: [PATCH] riscv: Correct a comment in io.h
>
> Replace NDS32 with RISC-V in the comments.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
>  arch/riscv/include/asm/io.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 220266e76f..b16e6dfa37 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -180,7 +180,7 @@ static inline u64 readq(const volatile void __iomem *addr)
>   *  IO port access primitives
>   *  -------------------------
>   *
> - * The NDS32 doesn't have special IO access instructions just like ARM;
> + * The RISC-V doesn't have special IO access instructions just like
> + ARM;
>   * all IO is memory mapped.
>   * Note that these are defined to perform little endian accesses
>   * only.  Their primary purpose is to access PCI and ISA peripherals.

Reviewed-by: Rick Chen <rick@andestech.com>
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 220266e76f..b16e6dfa37 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -180,7 +180,7 @@  static inline u64 readq(const volatile void __iomem *addr)
  *  IO port access primitives
  *  -------------------------
  *
- * The NDS32 doesn't have special IO access instructions just like ARM;
+ * The RISC-V doesn't have special IO access instructions just like ARM;
  * all IO is memory mapped.
  * Note that these are defined to perform little endian accesses
  * only.  Their primary purpose is to access PCI and ISA peripherals.