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Tue, 07 Mar 2023 21:16:29 -0800 (PST) From: Vasily Khoruzhick To: Simon Glass , Philipp Tomsich , Kever Yang , Lukasz Majewski , Sean Anderson , Mark Kettenis , u-boot@lists.denx.de Cc: Vasily Khoruzhick Subject: [PATCH v3 1/2] clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks Date: Tue, 7 Mar 2023 21:16:10 -0800 Message-Id: <20230308051611.80965-1-anarsoul@gmail.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang Signed-off-by: Vasily Khoruzhick --- v3: add r-b tag from Kever v2: implement stubs for CLK_PCIEPHY_REF instead of dropping assigned-clock properties drivers/clk/rockchip/clk_rk3568.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 253b69504f..1c6adc56f9 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; }