| Message ID | 20230307220827.68520-2-anarsoul@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | [v2,1/3] phy: rockchip-inno-usb2: add support for phy-supply | expand |
On 2023/3/8 06:08, Vasily Khoruzhick wrote: > Device tree contains assigned-clock-rates property for these, > but default value will work just fine > > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > v2: implement stubs for CLK_PCIEPHY_REF instead of dropping > assigned-clock properties > > drivers/clk/rockchip/clk_rk3568.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c > index 253b69504f..1c6adc56f9 100644 > --- a/drivers/clk/rockchip/clk_rk3568.c > +++ b/drivers/clk/rockchip/clk_rk3568.c > @@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) > case PCLK_PMU: > ret = rk3568_pmu_set_pmuclk(priv, rate); > break; > + case CLK_PCIEPHY0_REF: > + case CLK_PCIEPHY1_REF: > + return 0; > default: > return -ENOENT; > }
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 253b69504f..1c6adc56f9 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; }
Device tree contains assigned-clock-rates property for these, but default value will work just fine Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> --- v2: implement stubs for CLK_PCIEPHY_REF instead of dropping assigned-clock properties drivers/clk/rockchip/clk_rk3568.c | 3 +++ 1 file changed, 3 insertions(+)