From patchwork Mon Mar 6 14:53:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1752476 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=w8auVpRI; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=m3o556Ys; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PVhXG6s1sz246K for ; Tue, 7 Mar 2023 01:58:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5055F85DB9; Mon, 6 Mar 2023 15:56:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1678114593; bh=0+rgXoWATBoLDK4FFPSeqKLT7IYr6lT3VsKM6ShmDW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=w8auVpRIC6mBe/z+oJFudRtMwlUtiVfuNl3hVPCJ/sck9/cT2mPycwr7i4lTHxb+n PilgWBqxAb255fvkk33ywvZ3PWVJvs0XZJmakyyQP6MeMm/S1f+WlIWWFC5z29uqZz /ZhjnY83p3Qo/crR3aoXVZfNv1OQKqg5UkfGGIf064DNNFioXs3e7EE5qqn9FlrdzJ 3yuyPal96guItzR1LAIQ0McRWq3RM4rUQRNCIWKsqpR+GCsU+ImdfpdSE4Oim62uVC ffZDAxz4gh2lYaupVYCPhQ+wbibEO+4BHYwJNG5+CXZs+X/gkcv1FKpWVcchVRmngw 3v9dSjMkSO4cg== Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id B8441858FC; Mon, 6 Mar 2023 15:54:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1678114455; bh=0+rgXoWATBoLDK4FFPSeqKLT7IYr6lT3VsKM6ShmDW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m3o556Ys+eX6a9ccFz82sJ4mye0ASmUmS+YGj9/aCmEmH08tk66jEbXUXFAUDrJfC gS2Upclr4JBysMS0a+07+Znb/l1HtWjOxQzAubiUNxju3FhWdzduJC4AJN5pd3vTXP DM9MBmpQbcxiw0TXCakoKu7HSV6vaCbO9BDFdxDXEUZxLYd+y6EcT6NGRXET/lGHmH FU7KyCB+hQZmqOTgcyXIcyaSH/bOiBwQfFkX/RezjLqlYCn1+rfdM54ZE/pHeEXJa1 hXPIIkVSklmd+bio96YzF6+XBxE31nZNVjeTUFp75hs6FWU+7PbfkZGCA0c7OLwq46 nC99u0b3acSqA== From: Marek Vasut To: u-boot@lists.denx.de Cc: Marek Vasut , Ramon Fried , "Ariel D'Alessandro" , "NXP i.MX U-Boot Team" , Andrey Zhizhikin , Fabio Estevam , Joe Hershberger , Lukasz Majewski , Marcel Ziswiler , Michael Trimarchi , Peng Fan , Sean Anderson , Stefano Babic , Tim Harvey , Tommaso Merciai Subject: [PATCH v4 09/14] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus Date: Mon, 6 Mar 2023 15:53:49 +0100 Message-Id: <20230306145354.7439-9-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230306145354.7439-1-marex@denx.de> References: <20230306145354.7439-1-marex@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Implement common board_interface_eth_init() and call it from the DWMAC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Plus DWMAC and supersedes current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Reviewed-by: Ramon Fried Signed-off-by: Marek Vasut --- Cc: "Ariel D'Alessandro" Cc: "NXP i.MX U-Boot Team" Cc: Andrey Zhizhikin Cc: Fabio Estevam Cc: Joe Hershberger Cc: Lukasz Majewski Cc: Marcel Ziswiler Cc: Marek Vasut Cc: Michael Trimarchi Cc: Peng Fan Cc: Ramon Fried Cc: Sean Anderson Cc: Stefano Babic Cc: Tim Harvey Cc: Tommaso Merciai Cc: u-boot@lists.denx.de --- V2: - Add RB from Ramon - Handle RGMII_ID/RGMII_RXID/RGMII_TXID just like plain RGMII V3: Make the function more generic, so it can be shared by eqos and fec V4: No change --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 8 ++- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 59 +++++++++++++++++++++- drivers/net/dwc_eth_qos_imx.c | 4 ++ 3 files changed, 69 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 1559bf6d218..1818b459fa6 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -89,7 +89,13 @@ #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 -#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16) +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16) #define FEC_QUIRK_ENET_MAC #ifdef CONFIG_ARMV8_PSCI /* Final jump location */ diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 494bfbedc8c..1546c9ba9a0 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -825,7 +826,7 @@ u32 mxc_get_clock(enum mxc_clock clk) return 0; } -#ifdef CONFIG_DWC_ETH_QOS +#if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS) int set_clk_eqos(enum enet_freq type) { u32 target; @@ -872,6 +873,52 @@ int set_clk_eqos(enum enet_freq type) return 0; } + +static int imx8mp_eqos_interface_init(struct udevice *dev, + phy_interface_t interface_type) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + clrbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN); + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII); + break; + case PHY_INTERFACE_MODE_RMII: + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII); + break; + default: + return -EINVAL; + } + + return 0; +} +#else +static int imx8mp_eqos_interface_init(struct udevice *dev, + phy_interface_t interface_type) +{ + return 0; +} #endif #ifdef CONFIG_FEC_MXC @@ -922,3 +969,13 @@ int set_clk_enet(enum enet_freq type) return 0; } #endif + +int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) +{ + if (IS_ENABLED(CONFIG_IMX8MP) && + IS_ENABLED(CONFIG_DWC_ETH_QOS) && + device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos")) + return imx8mp_eqos_interface_init(dev, interface_type); + + return -EINVAL; +} diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 962c5373243..60f3f3f5a10 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -55,6 +55,10 @@ static int eqos_probe_resources_imx(struct udevice *dev) return -EINVAL; } + ret = board_interface_eth_init(dev, interface); + if (ret) + return -EINVAL; + eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);