Message ID | 20230220194927.476708-12-sjg@chromium.org |
---|---|
State | Superseded |
Delegated to: | Bin Meng |
Headers | show |
Series | x86: Various minor enhancements for coreboot | expand |
On Tue, Feb 21, 2023 at 3:49 AM Simon Glass <sjg@chromium.org> wrote: > > Enable this so that PCI devices can be used correctly without needing > to do a manual scan. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > configs/coreboot_defconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index d8c5be66ad7..1c5e7fc717d 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -18,6 +18,7 @@ CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y +CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y
Enable this so that PCI devices can be used correctly without needing to do a manual scan. Signed-off-by: Simon Glass <sjg@chromium.org> --- configs/coreboot_defconfig | 1 + 1 file changed, 1 insertion(+)