[v2,08/12] clk: uniphier: Add missing USB SS-PHY clocks

Message ID	20230201011325.10679-9-hayashi.kunihiko@socionext.com
State	Superseded
Delegated to:	Bin Meng
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> To: Marek Vasut <marex@denx.de>, Michal Simek <michal.simek@amd.com>, Sean Anderson <seanga2@gmail.com>, Angus Ainslie <angus@akkea.ca>, Lukasz Majewski <lukma@denx.de>, T Karthik Reddy <t.karthik.reddy@xilinx.com>, Jan Kiszka <jan.kiszka@siemens.com> Cc: u-boot@lists.denx.de, Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Subject: [PATCH v2 08/12] clk: uniphier: Add missing USB SS-PHY clocks Date: Wed, 1 Feb 2023 10:13:21 +0900 Message-Id: <20230201011325.10679-9-hayashi.kunihiko@socionext.com> In-Reply-To: <20230201011325.10679-1-hayashi.kunihiko@socionext.com> References: <20230201011325.10679-1-hayashi.kunihiko@socionext.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	usb: dwc3: Refactor dwc3-generic and apply to dwc3-uniphier \| expand [v2,00/12] usb: dwc3: Refactor dwc3-generic and apply to dwc3-uniphier [v2,01/12] usb: dwc3: Look up reference clock DT phandle in both controller DT nodes [v2,02/12] usb: dwc3-generic: Allow different controller DT node pattern [v2,03/12] usb: dwc3-generic: Add clock initialization in child DT node [v2,04/12] usb: dwc3-generic: Export glue structures and functions [v2,05/12] usb: dwc3-generic: Add the size of regs property to glue structure [v2,06/12] usb: dwc3-uniphier: Use dwc3-generic instead of xhci-dwc3 [v2,07/12] reset: uniphier: Add USB glue reset support [v2,08/12] clk: uniphier: Add missing USB SS-PHY clocks [v2,09/12] phy: socionext: Add UniPhier USB3 PHY driver [v2,10/12] ARM: dts: uniphier: Fix node names and missing reg property in USB glue node [v2,11/12] ARM: dts: uniphier: Switch USB node to the original [v2,12/12] uniphier_defconfig: Disable USB_XHCI_DWC3

Message ID

20230201011325.10679-9-hayashi.kunihiko@socionext.com

State

Superseded

Delegated to:

Bin Meng

Headers

From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Marek Vasut <marex@denx.de>, Michal Simek <michal.simek@amd.com>,
 Sean Anderson <seanga2@gmail.com>, Angus Ainslie <angus@akkea.ca>,
 Lukasz Majewski <lukma@denx.de>,
 T Karthik Reddy <t.karthik.reddy@xilinx.com>,
 Jan Kiszka <jan.kiszka@siemens.com>
Cc: u-boot@lists.denx.de,
	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH v2 08/12] clk: uniphier: Add missing USB SS-PHY clocks
Date: Wed,  1 Feb 2023 10:13:21 +0900
Message-Id: <20230201011325.10679-9-hayashi.kunihiko@socionext.com>
In-Reply-To: <20230201011325.10679-1-hayashi.kunihiko@socionext.com>
References: <20230201011325.10679-1-hayashi.kunihiko@socionext.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

usb: dwc3: Refactor dwc3-generic and apply to dwc3-uniphier | expand

Commit Message

Kunihiko Hayashi Feb. 1, 2023, 1:13 a.m. UTC

The USB SS-PHY needs its own clock, however, some clocks don't have
clock gates. Define missing clock entries for the PHY as reference
clock.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index ff5d364f59..3b8595fe61 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -28,7 +28,10 @@  const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16),	/* usb30 (Pro4, Pro5, PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17),	/* usb31 (Pro4, Pro5, PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19),	/* usb30-phy (PXs2) */
+	UNIPHIER_CLK_RATE(17, 25000000),		/* usb30-phy2 (PXs2) */
+	UNIPHIER_CLK_RATE(18, 25000000),		/* usb30-phy3 (PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20),	/* usb31-phy (PXs2) */
+	UNIPHIER_CLK_RATE(21, 25000000),		/* usb31-phy2 (PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2),	/* pcie (Pro5) */
 	{ /* sentinel */ }
 #endif
@@ -44,6 +47,8 @@  const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),	/* usb30 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),	/* usb30-phy0 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13),	/* usb30-phy1 (LD20) */
+	UNIPHIER_CLK_RATE(18, 25000000),		/* usb30-phy2 (LD20) */
+	UNIPHIER_CLK_RATE(19, 25000000),		/* usb30-phy3 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4),	/* pcie */
 	{ /* sentinel */ }
 #endif

[v2,08/12] clk: uniphier: Add missing USB SS-PHY clocks

Commit Message

Patch