@@ -29,7 +29,7 @@ int platform_sys_info(struct sys_info *si)
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86XX)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC83XX)
#define bi_bar bi_immrbar
@@ -2,4 +2,4 @@
obj-$(CONFIG_MPC83XX) += mpc8xxx/
obj-$(CONFIG_MPC85XX) += mpc8xxx/
-obj-$(CONFIG_MPC86xx) += mpc8xxx/
+obj-$(CONFIG_MPC86XX) += mpc8xxx/
@@ -18,7 +18,7 @@ obj-$(CONFIG_FSL_LAW) += law.o
else
obj-$(CONFIG_MPC85XX) += cpu.o
-obj-$(CONFIG_MPC86xx) += cpu.o
+obj-$(CONFIG_MPC86XX) += cpu.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
@@ -94,7 +94,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(C291, C291, 1),
CPU_TYPE_ENTRY(C292, C292, 1),
CPU_TYPE_ENTRY(C293, C293, 1),
-#elif defined(CONFIG_MPC86xx)
+#elif defined(CONFIG_MPC86XX)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
CPU_TYPE_ENTRY(8641D, 8641D, 2),
@@ -17,7 +17,7 @@
#include <phy.h>
#include <hwconfig.h>
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx))
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
{
int off, ret = -FDT_ERR_NOTFOUND;
@@ -69,7 +69,7 @@ void ft_fixup_num_cores(void *blob) {
debug ("deleted %d extra core entry entries from device tree\n",
del_cores);
}
-#endif /* defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx) */
+#endif /* defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX) */
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
@@ -39,10 +39,10 @@
#define _DEVDISR_SRIO2 MPC85XX_DEVDISR_SRIO
#define _DEVDISR_RMU MPC85XX_DEVDISR_RMSG
#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85XX_GUTS_ADDR
-#elif defined(CONFIG_MPC86xx)
- #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
- #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
- #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
+#elif defined(CONFIG_MPC86XX)
+ #define _DEVDISR_SRIO1 MPC86XX_DEVDISR_SRIO
+ #define _DEVDISR_SRIO2 MPC86XX_DEVDISR_SRIO
+ #define _DEVDISR_RMU MPC86XX_DEVDISR_RMSG
#define CFG_SYS_MPC8xxx_GUTS_ADDR \
(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
#else
@@ -16,7 +16,7 @@
#ifndef CFG_MAX_MEM_MAPPED
#if defined(CONFIG_E500) || \
- defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_MPC86XX) || \
defined(CONFIG_E300)
#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#else
@@ -258,7 +258,7 @@ int fsl_pcie_init_board(int busno);
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP; \
FT_FSL_PCIE3_SETUP;
-#elif defined(CONFIG_MPC86xx)
+#elif defined(CONFIG_MPC86XX)
#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
#define FT_FSL_PCI_SETUP \
@@ -53,12 +53,12 @@ struct arch_global_data {
# endif /* CONFIG_ARCH_MPC8360 */
#endif
#endif
-#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX)
u32 lbc_clk;
void *cpu;
-#endif /* CONFIG_MPC85XX || CONFIG_MPC86xx */
+#endif /* CONFIG_MPC85XX || CONFIG_MPC86XX */
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85XX) || \
- defined(CONFIG_MPC86xx)
+ defined(CONFIG_MPC86XX)
u32 i2c1_clk;
u32 i2c2_clk;
#endif
@@ -51,7 +51,7 @@ static inline uint get_svr(void)
}
#if defined(CONFIG_MPC85XX) || \
- defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_MPC86XX) || \
defined(CONFIG_MPC83XX)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
@@ -84,9 +84,9 @@ void get_sys_info(sys_info_t *);
void ft_fixup_cpu(void *, u64);
void ft_fixup_num_cores(void *);
#endif
-#if defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC86XX)
ulong get_bus_freq(ulong);
-typedef MPC86xx_SYS_INFO sys_info_t;
+typedef MPC86XX_SYS_INFO sys_info_t;
void get_sys_info(sys_info_t *);
static inline ulong get_ddr_freq(ulong dummy)
{
@@ -569,7 +569,7 @@
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#define ESR_ST 0x00800000 /* Store Operation */
-#if defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC86XX)
#define SPRN_MSSCR0 0x3f6
#define SPRN_MSSSR0 0x3f7
#endif
@@ -646,10 +646,10 @@
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
-#if defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC86XX)
#define MSSCR0 SPRN_MSSCR0
#endif
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86XX)
#define PIR SPRN_PIR
#endif
#define SVR SPRN_SVR /* System-On-Chip Version Register */
@@ -1156,7 +1156,7 @@ int fixup_cpu(void);
int fsl_qoriq_core_to_cluster(unsigned int core);
int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
-#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX)
#define CPU_TYPE_ENTRY(n, v, nc) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
.mask = (1 << (nc)) - 1 }
@@ -16,7 +16,7 @@ int arch_setup_bdinfo(void)
{
struct bd_info *bd = gd->bd;
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86XX)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
@@ -293,7 +293,7 @@ void boot_prep_vxworks(struct bootm_headers *images)
#if defined(CONFIG_MPC85XX)
ft_fixup_cpu(images->ft_addr, base + size);
ft_fixup_num_cores(images->ft_addr);
-#elif defined(CONFIG_MPC86xx)
+#elif defined(CONFIG_MPC86XX)
off = fdt_add_mem_rsv(images->ft_addr,
determine_mp_bootpg(NULL), (u64)4096);
if (off < 0)
@@ -64,7 +64,7 @@ ppcSync:
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
-#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -88,7 +88,7 @@ _GLOBAL(flush_dcache_range)
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -34,7 +34,7 @@ int arch_reserve_stacks(void)
int arch_setup_dest_addr(void)
{
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86XX) || defined(CONFIG_E500))
/*
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
@@ -3,8 +3,8 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
+obj-$(CONFIG_MPC86XX) += fsl_8xxx_clk.o
obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC85XX) += fsl_8xxx_misc.o board.o
-obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
+obj-$(CONFIG_MPC86XX) += fsl_8xxx_misc.o board.o
obj-$(CONFIG_NAND_ACTL) += actl_nand.o
@@ -14,7 +14,7 @@ unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85XX)
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85XX_GUTS_ADDR);
-#elif defined(CONFIG_MPC86xx)
+#elif defined(CONFIG_MPC86XX)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
@@ -29,7 +29,7 @@ uint get_board_derivative(void)
{
#if defined(CONFIG_MPC85XX)
volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85XX_GUTS_ADDR;
-#elif defined(CONFIG_MPC86xx)
+#elif defined(CONFIG_MPC86XX)
volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
@@ -130,7 +130,7 @@ static int initr_reloc_global_data(void)
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
#endif
-#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85XX) || defined(CONFIG_MPC86XX)
/*
* The gd->cpu pointer is set to an address in flash before relocation.
* We need to update it to point to the same CPU entry in RAM.
@@ -96,7 +96,7 @@ config SYS_FSL_DDRC_GEN1
config SYS_FSL_DDRC_GEN2
bool
- depends on !MPC86xx
+ depends on !MPC86XX
help
Enable Freescale DDR2 controller.
@@ -153,7 +153,7 @@ config SYS_FSL_DDR2
bool "Freescale DDR2 controller"
depends on SYS_FSL_HAS_DDR2
imply DDR_SPD
- select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
+ select SYS_FSL_DDRC_GEN2 if (!MPC86XX && !SYS_FSL_DDRC_GEN3)
config SYS_FSL_DDR1
bool "Freescale DDR1 controller"
@@ -27,8 +27,8 @@
dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83XX_DMA_ADDR);
#elif defined(CONFIG_MPC85XX)
ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85XX_DMA_ADDR);
-#elif defined(CONFIG_MPC86xx)
-ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+#elif defined(CONFIG_MPC86XX)
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86XX_DMA_ADDR);
#else
#error "Freescale DMA engine not supported on your processor"
#endif
@@ -37,7 +37,7 @@ static void dma_sync(void)
{
#if defined(CONFIG_MPC85XX)
asm("sync; isync; msync");
-#elif defined(CONFIG_MPC86xx)
+#elif defined(CONFIG_MPC86XX)
asm("sync; isync");
#endif
}
@@ -150,7 +150,7 @@ config PCIE_FSL
select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240
help
Say Y here if you want to enable PCIe controller support on FSL
- PowerPC MPC85XX, MPC86xx, B series, P series and T series SoCs.
+ PowerPC MPC85XX, MPC86XX, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
config PCI_MPC85XX
@@ -116,7 +116,7 @@ config ENV_IS_IN_FLASH
default y if ARCH_INTEGRATOR_CP
default y if M548x || M547x || M5282
default y if MCF532X || MCF52x2
- default y if MPC86xx || MPC83XX
+ default y if MPC86XX || MPC83XX
default y if ARCH_MPC8548
default y if SH && !CPU_SH4
help
@@ -37,7 +37,7 @@ struct bd_info {
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86XX)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_M68K)
@@ -4,8 +4,8 @@
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*/
-#ifndef __MPC86xx_H__
-#define __MPC86xx_H__
+#ifndef __MPC86XX_H__
+#define __MPC86XX_H__
#include <asm/fsl_lbc.h>
@@ -44,7 +44,7 @@ typedef struct {
unsigned long freq_processor;
unsigned long freq_systembus;
unsigned long freq_localbus;
-} MPC86xx_SYS_INFO;
+} MPC86XX_SYS_INFO;
#define l1icache_enable icache_enable
@@ -87,4 +87,4 @@ void setup_ddr_bat(phys_addr_t dram_size);
extern void setup_bats(void);
#endif /* _ASMLANGUAGE */
-#endif /* __MPC86xx_H__ */
+#endif /* __MPC86XX_H__ */
@@ -28,7 +28,7 @@ extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85XX) || \
- defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_MPC86XX) || \
defined(CONFIG_ARCH_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
CONFIG options must not use lower-case letter. Convert this to upper case. Signed-off-by: Simon Glass <sjg@chromium.org> --- (no changes since v1) api/api_platform-powerpc.c | 2 +- arch/powerpc/cpu/Makefile | 2 +- arch/powerpc/cpu/mpc8xxx/Makefile | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 2 +- arch/powerpc/cpu/mpc8xxx/fdt.c | 4 ++-- arch/powerpc/cpu/mpc8xxx/srio.c | 8 ++++---- arch/powerpc/include/asm/config.h | 2 +- arch/powerpc/include/asm/fsl_pci.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 +++--- arch/powerpc/include/asm/ppc.h | 6 +++--- arch/powerpc/include/asm/processor.h | 8 ++++---- arch/powerpc/lib/bdinfo.c | 2 +- arch/powerpc/lib/bootm.c | 2 +- arch/powerpc/lib/ppccache.S | 4 ++-- arch/powerpc/lib/stack.c | 2 +- board/xes/common/Makefile | 4 ++-- board/xes/common/fsl_8xxx_clk.c | 2 +- board/xes/common/fsl_8xxx_misc.c | 2 +- common/board_r.c | 2 +- drivers/ddr/fsl/Kconfig | 4 ++-- drivers/dma/fsl_dma.c | 6 +++--- drivers/pci/Kconfig | 2 +- env/Kconfig | 2 +- include/asm-generic/u-boot.h | 2 +- include/mpc86xx.h | 8 ++++---- include/serial.h | 2 +- 26 files changed, 45 insertions(+), 45 deletions(-)