| Message ID | 20230118084400.15859-3-clamor95@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Tom Warren |
| Headers | show |
| Series | Timer support for ARM Tegra | expand |
Hi Svyatoslav, On Wed, 18 Jan 2023 at 01:44, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > Add timer support for T20/T30/T114 and T124 based devices. > Driver is based on DM, has device tree support and can be > used on SPL and early boot stage. > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 > Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 > Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > --- > > Changed in v4: > - removed BOOTSTAGE ifdefs > - use early timer on boot stage unconditionally > --- > drivers/timer/Kconfig | 8 +++ > drivers/timer/Makefile | 1 + > drivers/timer/tegra-timer.c | 113 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 122 insertions(+) > create mode 100644 drivers/timer/tegra-timer.c > > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > index 6d6665005c..f32bd16227 100644 > --- a/drivers/timer/Kconfig > +++ b/drivers/timer/Kconfig > @@ -252,6 +252,14 @@ config STM32_TIMER > Select this to enable support for the timer found on > STM32 devices. > > +config TEGRA_TIMER > + bool "Tegra timer support" > + depends on TIMER > + select TIMER_EARLY > + help > + Select this to enable support for the timer found on > + Tegra devices. > + > config X86_TSC_TIMER > bool "x86 Time-Stamp Counter (TSC) timer support" > depends on TIMER && X86 > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > index 6470fd5426..3c92113fc6 100644 > --- a/drivers/timer/Makefile > +++ b/drivers/timer/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > obj-$(CONFIG_MTK_TIMER) += mtk_timer.o > obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > new file mode 100644 > index 0000000000..f0d8ba727d > --- /dev/null > +++ b/drivers/timer/tegra-timer.c > @@ -0,0 +1,113 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <errno.h> > +#include <timer.h> > + > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/tegra.h> > + > +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) > +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) > + > +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) > +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) > + > +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ > + > +u64 notrace timer_early_get_count(void) > +{ > + /* At this stage raw timer is used */ > + return readl(TEGRA_TIMER_USEC_CNTR); > +} > + > +unsigned long notrace timer_early_get_rate(void) > +{ > + return TEGRA_TIMER_RATE; Is that the rate at reset, before the timer is inited? Remember this is called before your probe() function. If not, you will need to init it first here. > +} > + > +ulong timer_get_boot_us(void) > +{ > + return timer_early_get_count(); > +} > + > +static notrace u64 tegra_timer_get_count(struct udevice *dev) > +{ > + u32 val = timer_early_get_count(); > + return timer_conv_64(val); Here you are ignoring the probed timing, if available. You should really use uc_priv->clock_rate > +} > + Regards, Simon
ср, 18 січ. 2023 р. о 21:42 Simon Glass <sjg@chromium.org> пише: > > Hi Svyatoslav, > > On Wed, 18 Jan 2023 at 01:44, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > > > Add timer support for T20/T30/T114 and T124 based devices. > > Driver is based on DM, has device tree support and can be > > used on SPL and early boot stage. > > > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 > > Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 > > Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > > --- > > > > Changed in v4: > > - removed BOOTSTAGE ifdefs > > - use early timer on boot stage unconditionally > > --- > > drivers/timer/Kconfig | 8 +++ > > drivers/timer/Makefile | 1 + > > drivers/timer/tegra-timer.c | 113 ++++++++++++++++++++++++++++++++++++ > > 3 files changed, 122 insertions(+) > > create mode 100644 drivers/timer/tegra-timer.c > > > > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > > index 6d6665005c..f32bd16227 100644 > > --- a/drivers/timer/Kconfig > > +++ b/drivers/timer/Kconfig > > @@ -252,6 +252,14 @@ config STM32_TIMER > > Select this to enable support for the timer found on > > STM32 devices. > > > > +config TEGRA_TIMER > > + bool "Tegra timer support" > > + depends on TIMER > > + select TIMER_EARLY > > + help > > + Select this to enable support for the timer found on > > + Tegra devices. > > + > > config X86_TSC_TIMER > > bool "x86 Time-Stamp Counter (TSC) timer support" > > depends on TIMER && X86 > > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > > index 6470fd5426..3c92113fc6 100644 > > --- a/drivers/timer/Makefile > > +++ b/drivers/timer/Makefile > > @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o > > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > > obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o > > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > > +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o > > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > > obj-$(CONFIG_MTK_TIMER) += mtk_timer.o > > obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o > > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > > new file mode 100644 > > index 0000000000..f0d8ba727d > > --- /dev/null > > +++ b/drivers/timer/tegra-timer.c > > @@ -0,0 +1,113 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> > > + */ > > + > > +#include <common.h> > > +#include <dm.h> > > +#include <errno.h> > > +#include <timer.h> > > + > > +#include <asm/io.h> > > +#include <asm/arch/clock.h> > > +#include <asm/arch/tegra.h> > > + > > +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) > > +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) > > + > > +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) > > +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) > > + > > +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ > > + > > +u64 notrace timer_early_get_count(void) > > +{ > > + /* At this stage raw timer is used */ > > + return readl(TEGRA_TIMER_USEC_CNTR); > > +} > > + > > +unsigned long notrace timer_early_get_rate(void) > > +{ > > + return TEGRA_TIMER_RATE; > > Is that the rate at reset, before the timer is inited? Remember this > is called before your probe() function. > > If not, you will need to init it first here. It has to be 1 MHz left by the primary bootloader (bootrom). In the case of reset default value set is 1/13 of osc clock. Unfortunately at this stage we can not determine the exact osc clock since it is in the clock and reset device (which itself can not be ready). Pre-dm timer might not be explicitly precise but it works fine on early stages with providing delays. > > +} > > + > > +ulong timer_get_boot_us(void) > > +{ > > + return timer_early_get_count(); > > +} > > + > > +static notrace u64 tegra_timer_get_count(struct udevice *dev) > > +{ > > + u32 val = timer_early_get_count(); > > + return timer_conv_64(val); > > Here you are ignoring the probed timing, if available. You should > really use uc_priv->clock_rate > At this point the timer is already probed and configured to have a precise 1MHz clock. Tegra timer has a step of 1 microsecond. U-Boot documentation of timer suggested to refer to sandbox timer and sandbox timer get_count uses microsecond cont. https://github.com/u-boot/u-boot/blob/a94ab561e2f49a80d8579930e840b810ab1a1330/drivers/timer/sandbox_timer.c#L24 os_get_nsec() / 1000 which is nanosec / 1000 = microsecond > > +} > > + > > Regards, > Simon
Hi Svyatoslav, On Thu, 19 Jan 2023 at 00:12, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > ср, 18 січ. 2023 р. о 21:42 Simon Glass <sjg@chromium.org> пише: > > > > Hi Svyatoslav, > > > > On Wed, 18 Jan 2023 at 01:44, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > > > > > Add timer support for T20/T30/T114 and T124 based devices. > > > Driver is based on DM, has device tree support and can be > > > used on SPL and early boot stage. > > > > > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 > > > Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 > > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 > > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 > > > Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > > Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > > > > --- > > > > > > Changed in v4: > > > - removed BOOTSTAGE ifdefs > > > - use early timer on boot stage unconditionally > > > --- > > > drivers/timer/Kconfig | 8 +++ > > > drivers/timer/Makefile | 1 + > > > drivers/timer/tegra-timer.c | 113 ++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 122 insertions(+) > > > create mode 100644 drivers/timer/tegra-timer.c > > > > > > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > > > index 6d6665005c..f32bd16227 100644 > > > --- a/drivers/timer/Kconfig > > > +++ b/drivers/timer/Kconfig > > > @@ -252,6 +252,14 @@ config STM32_TIMER > > > Select this to enable support for the timer found on > > > STM32 devices. > > > > > > +config TEGRA_TIMER > > > + bool "Tegra timer support" > > > + depends on TIMER > > > + select TIMER_EARLY > > > + help > > > + Select this to enable support for the timer found on > > > + Tegra devices. > > > + > > > config X86_TSC_TIMER > > > bool "x86 Time-Stamp Counter (TSC) timer support" > > > depends on TIMER && X86 > > > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > > > index 6470fd5426..3c92113fc6 100644 > > > --- a/drivers/timer/Makefile > > > +++ b/drivers/timer/Makefile > > > @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o > > > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > > > obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o > > > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > > > +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o > > > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > > > obj-$(CONFIG_MTK_TIMER) += mtk_timer.o > > > obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o > > > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > > > new file mode 100644 > > > index 0000000000..f0d8ba727d > > > --- /dev/null > > > +++ b/drivers/timer/tegra-timer.c > > > @@ -0,0 +1,113 @@ > > > +// SPDX-License-Identifier: GPL-2.0+ > > > +/* > > > + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> > > > + */ > > > + > > > +#include <common.h> > > > +#include <dm.h> > > > +#include <errno.h> > > > +#include <timer.h> > > > + > > > +#include <asm/io.h> > > > +#include <asm/arch/clock.h> > > > +#include <asm/arch/tegra.h> > > > + > > > +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) > > > +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) > > > + > > > +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) > > > +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) > > > + > > > +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ > > > + > > > +u64 notrace timer_early_get_count(void) > > > +{ > > > + /* At this stage raw timer is used */ > > > + return readl(TEGRA_TIMER_USEC_CNTR); > > > +} > > > + > > > +unsigned long notrace timer_early_get_rate(void) > > > +{ > > > + return TEGRA_TIMER_RATE; > > > > Is that the rate at reset, before the timer is inited? Remember this > > is called before your probe() function. > > > > If not, you will need to init it first here. > > It has to be 1 MHz left by the primary bootloader (bootrom). > In the case of reset default value set is 1/13 of osc clock. > Unfortunately at this stage we can not determine the exact osc clock > since it is in the clock and reset device (which itself can not be > ready). Pre-dm timer might not be explicitly precise but it works fine > on early stages with providing delays. > > > > +} > > > + > > > +ulong timer_get_boot_us(void) > > > +{ > > > + return timer_early_get_count(); > > > +} > > > + > > > +static notrace u64 tegra_timer_get_count(struct udevice *dev) > > > +{ > > > + u32 val = timer_early_get_count(); > > > + return timer_conv_64(val); > > > > Here you are ignoring the probed timing, if available. You should > > really use uc_priv->clock_rate > > > > At this point the timer is already probed and configured to have a > precise 1MHz clock. Tegra timer has a step of 1 microsecond. > > U-Boot documentation of timer suggested to refer to sandbox timer and > sandbox timer get_count uses microsecond cont. > > https://github.com/u-boot/u-boot/blob/a94ab561e2f49a80d8579930e840b810ab1a1330/drivers/timer/sandbox_timer.c#L24 > > os_get_nsec() / 1000 which is nanosec / 1000 = microsecond That sounds OK. Then can you please add a few comments as to why you are ignoring the clock_rate? It will confuse other people who copy your driver? Mentioning the boot ROM, etc. helps too. With that, please add: Reviewed-by: Simon Glass <sjg@chromium.org> Regards, Simon
чт, 19 січ. 2023 р. о 18:19 Simon Glass <sjg@chromium.org> пише: > > Hi Svyatoslav, > > On Thu, 19 Jan 2023 at 00:12, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > > > ср, 18 січ. 2023 р. о 21:42 Simon Glass <sjg@chromium.org> пише: > > > > > > Hi Svyatoslav, > > > > > > On Wed, 18 Jan 2023 at 01:44, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > > > > > > > Add timer support for T20/T30/T114 and T124 based devices. > > > > Driver is based on DM, has device tree support and can be > > > > used on SPL and early boot stage. > > > > > > > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 > > > > Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 > > > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 > > > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 > > > > Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > > > Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > > > > > > --- > > > > > > > > Changed in v4: > > > > - removed BOOTSTAGE ifdefs > > > > - use early timer on boot stage unconditionally > > > > --- > > > > drivers/timer/Kconfig | 8 +++ > > > > drivers/timer/Makefile | 1 + > > > > drivers/timer/tegra-timer.c | 113 ++++++++++++++++++++++++++++++++++++ > > > > 3 files changed, 122 insertions(+) > > > > create mode 100644 drivers/timer/tegra-timer.c > > > > > > > > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > > > > index 6d6665005c..f32bd16227 100644 > > > > --- a/drivers/timer/Kconfig > > > > +++ b/drivers/timer/Kconfig > > > > @@ -252,6 +252,14 @@ config STM32_TIMER > > > > Select this to enable support for the timer found on > > > > STM32 devices. > > > > > > > > +config TEGRA_TIMER > > > > + bool "Tegra timer support" > > > > + depends on TIMER > > > > + select TIMER_EARLY > > > > + help > > > > + Select this to enable support for the timer found on > > > > + Tegra devices. > > > > + > > > > config X86_TSC_TIMER > > > > bool "x86 Time-Stamp Counter (TSC) timer support" > > > > depends on TIMER && X86 > > > > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > > > > index 6470fd5426..3c92113fc6 100644 > > > > --- a/drivers/timer/Makefile > > > > +++ b/drivers/timer/Makefile > > > > @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o > > > > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > > > > obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o > > > > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > > > > +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o > > > > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > > > > obj-$(CONFIG_MTK_TIMER) += mtk_timer.o > > > > obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o > > > > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > > > > new file mode 100644 > > > > index 0000000000..f0d8ba727d > > > > --- /dev/null > > > > +++ b/drivers/timer/tegra-timer.c > > > > @@ -0,0 +1,113 @@ > > > > +// SPDX-License-Identifier: GPL-2.0+ > > > > +/* > > > > + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> > > > > + */ > > > > + > > > > +#include <common.h> > > > > +#include <dm.h> > > > > +#include <errno.h> > > > > +#include <timer.h> > > > > + > > > > +#include <asm/io.h> > > > > +#include <asm/arch/clock.h> > > > > +#include <asm/arch/tegra.h> > > > > + > > > > +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) > > > > +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) > > > > + > > > > +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) > > > > +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) > > > > + > > > > +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ > > > > + > > > > +u64 notrace timer_early_get_count(void) > > > > +{ > > > > + /* At this stage raw timer is used */ > > > > + return readl(TEGRA_TIMER_USEC_CNTR); > > > > +} > > > > + > > > > +unsigned long notrace timer_early_get_rate(void) > > > > +{ > > > > + return TEGRA_TIMER_RATE; > > > > > > Is that the rate at reset, before the timer is inited? Remember this > > > is called before your probe() function. > > > > > > If not, you will need to init it first here. > > > > It has to be 1 MHz left by the primary bootloader (bootrom). > > In the case of reset default value set is 1/13 of osc clock. > > Unfortunately at this stage we can not determine the exact osc clock > > since it is in the clock and reset device (which itself can not be > > ready). Pre-dm timer might not be explicitly precise but it works fine > > on early stages with providing delays. > > > > > > +} > > > > + > > > > +ulong timer_get_boot_us(void) > > > > +{ > > > > + return timer_early_get_count(); > > > > +} > > > > + > > > > +static notrace u64 tegra_timer_get_count(struct udevice *dev) > > > > +{ > > > > + u32 val = timer_early_get_count(); > > > > + return timer_conv_64(val); > > > > > > Here you are ignoring the probed timing, if available. You should > > > really use uc_priv->clock_rate > > > > > > > At this point the timer is already probed and configured to have a > > precise 1MHz clock. Tegra timer has a step of 1 microsecond. > > > > U-Boot documentation of timer suggested to refer to sandbox timer and > > sandbox timer get_count uses microsecond cont. > > > > https://github.com/u-boot/u-boot/blob/a94ab561e2f49a80d8579930e840b810ab1a1330/drivers/timer/sandbox_timer.c#L24 > > > > os_get_nsec() / 1000 which is nanosec / 1000 = microsecond > > That sounds OK. Then can you please add a few comments as to why you > are ignoring the clock_rate? It will confuse other people who copy > your driver? Mentioning the boot ROM, etc. helps too. > > With that, please add: > > Reviewed-by: Simon Glass <sjg@chromium.org> > > Regards, > Simon Thank you! Will do it as soon as possible. Best regards, Svyatoslav R.
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6d6665005c..f32bd16227 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -252,6 +252,14 @@ config STM32_TIMER Select this to enable support for the timer found on STM32 devices. +config TEGRA_TIMER + bool "Tegra timer support" + depends on TIMER + select TIMER_EARLY + help + Select this to enable support for the timer found on + Tegra devices. + config X86_TSC_TIMER bool "x86 Time-Stamp Counter (TSC) timer support" depends on TIMER && X86 diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 6470fd5426..3c92113fc6 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c new file mode 100644 index 0000000000..f0d8ba727d --- /dev/null +++ b/drivers/timer/tegra-timer.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/tegra.h> + +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) + +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) + +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ + +u64 notrace timer_early_get_count(void) +{ + /* At this stage raw timer is used */ + return readl(TEGRA_TIMER_USEC_CNTR); +} + +unsigned long notrace timer_early_get_rate(void) +{ + return TEGRA_TIMER_RATE; +} + +ulong timer_get_boot_us(void) +{ + return timer_early_get_count(); +} + +static notrace u64 tegra_timer_get_count(struct udevice *dev) +{ + u32 val = timer_early_get_count(); + return timer_conv_64(val); +} + +static int tegra_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + u32 usec_config, value; + + /* Timer rate has to be set unconditionally */ + uc_priv->clock_rate = TEGRA_TIMER_RATE; + + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_13_0: + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case CLOCK_OSC_FREQ_19_2: + usec_config = 0x045f; /* (95+1)/(4+1) */ + break; + case CLOCK_OSC_FREQ_12_0: + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case CLOCK_OSC_FREQ_26_0: + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case CLOCK_OSC_FREQ_16_8: + usec_config = 0x0453; /* (83+1)/(4+1) */ + break; + case CLOCK_OSC_FREQ_38_4: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case CLOCK_OSC_FREQ_48_0: + usec_config = 0x002f; /* (47+1)/(0+1) */ + break; + default: + return -EINVAL; + } + + /* Enable clock to timer hardware */ + value = readl_relaxed(TEGRA_OSC_CLK_ENB_L_SET); + writel_relaxed(value | TEGRA_OSC_SET_CLK_ENB_TMR, + TEGRA_OSC_CLK_ENB_L_SET); + + writel_relaxed(usec_config, TEGRA_TIMER_USEC_CFG); + + return 0; +} + +static const struct timer_ops tegra_timer_ops = { + .get_count = tegra_timer_get_count, +}; + +static const struct udevice_id tegra_timer_ids[] = { + { .compatible = "nvidia,tegra20-timer" }, + { .compatible = "nvidia,tegra30-timer" }, + { .compatible = "nvidia,tegra114-timer" }, + { .compatible = "nvidia,tegra124-timer" }, + { } +}; + +U_BOOT_DRIVER(tegra_timer) = { + .name = "tegra_timer", + .id = UCLASS_TIMER, + .of_match = tegra_timer_ids, + .probe = tegra_timer_probe, + .ops = &tegra_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +};