From patchwork Mon Dec 12 13:39:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 1714998 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=1nb1MiaZ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NW2rt6pYfz240J for ; Tue, 13 Dec 2022 00:43:26 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AE44A85449; Mon, 12 Dec 2022 14:42:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="1nb1MiaZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 81B7C8544B; Mon, 12 Dec 2022 14:42:18 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 26B388544A for ; Mon, 12 Dec 2022 14:42:09 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Sergiu.Moga@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670852530; x=1702388530; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=FqIqzLWJBXugH3Uxvp8lOVLcMZCmrlRH4kJNSCLbJZ0=; b=1nb1MiaZMveU+/11gwGT3+HuyBWos6q6oLRMBlAep7GawHJUz+NsnUIy 0Ds42ke9Kz8bupdJBFl0uVYz7v8JTqnTuTwZhh4Hjg3e4Yn7NNajtQ2pk hirB7hIfKIxWcH9UvHR+ttj8S9wY5PGYM6tWthlc6hhWiGTgHKR7YYId/ rtQgiTglD3MFp2riDc4fZYdwHk2inD9gls4ReiFO1IZVaTNQjGTy6igbp AlrKvQ0luhxXqzeJAgXviqN5JtTWAtAfl475ujqcSbKJoxqBwOjNX6FS6 R5OcA+mnTp9sP7ALAC3Ryj99UeTHHtuyLYZp2JHUsAkEiLizk2oOapoxc A==; X-IronPort-AV: E=Sophos;i="5.96,238,1665471600"; d="scan'208";a="127693849" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Dec 2022 06:42:08 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 12 Dec 2022 06:42:07 -0700 Received: from ROB-ULT-M68701.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Mon, 12 Dec 2022 06:42:01 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 10/19] ARM: at91: add sama7 SFR definitions Date: Mon, 12 Dec 2022 15:39:41 +0200 Message-ID: <20221212133949.226246-11-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221212133949.226246-1-sergiu.moga@microchip.com> References: <20221212133949.226246-1-sergiu.moga@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Cristian Birsan Special Function Registers(SFR) definitions for SAMA7 product family. Signed-off-by: Cristian Birsan Signed-off-by: Sergiu Moga --- v1 -> v3: - No change arch/arm/mach-at91/include/mach/sama7-sfr.h | 59 +++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/sama7-sfr.h diff --git a/arch/arm/mach-at91/include/mach/sama7-sfr.h b/arch/arm/mach-at91/include/mach/sama7-sfr.h new file mode 100644 index 0000000000..a987ff5465 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7-sfr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Microchip SFR (Special Function Registers) registers for SAMA7 family. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Cristian Birsan + */ + +#ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H +#define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H + +#define SAMA7_SFR_OHCIICR 0x00 /* OHCI INT Configuration Register */ +#define SAMA7_SFR_OHCIISR 0x04 /* OHCI INT Status Register */ +/* 0x08 ~ 0xe3: Reserved */ +#define SAMA7_SFR_WPMR 0xe4 /* Write Protection Mode Register */ +#define SAMA7_SFR_WPSR 0xe4 /* Write Protection Status Register */ +/* 0xec ~ 0x200b: Reserved */ +#define SAMA7_SFR_DEBUG 0x200c /* Debug Register */ + +/* 0x2010 ~ 0x2027: Reserved */ +#define SAMA7_SFR_EHCIOHCI 0x2020 /* EHCI OHCI Clock Configuration Reg */ + +#define SAMA7_SFR_HSS_AXI_QOS 0x2028 /* HSS AXI QOS Register */ +#define SAMA7_SFR_UDDRC 0x202c /* UDDRC Register */ +#define SAMA7_SFR_CAN_SRAM_SEL 0x2030 /* CAN SRAM Select. Register */ +/* 0x2034 ~ 0x203f: Reserved */ + +#define SAMA7_SFR_UTMI0 0x2040 +#define SAMA7_SFR_UTMI0R(x) (SAMA7_SFR_UTMI0 + 4 * (x)) + +#define SAMA7_SFR_UTMI0R0 0x2040 /* UTMI0 Configuration Register */ +#define SAMA7_SFR_UTMI0R1 0x2044 /* UTMI1 Configuration Register */ +#define SAMA7_SFR_UTMI0R2 0x2048 /* UTMI2 Configuration Register */ + +/* Field definitions */ +#define SAMA7_SFR_OHCIICR_ARIE BIT(0) +#define SAMA7_SFR_OHCIICR_APPSTART BIT(1) +#define SAMA7_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define SAMA7_SFR_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define SAMA7_SFR_OHCIISR_RIS(x) BIT(x) + +#define SAMA7_SFR_WPMR_WPEN BIT(0) +#define SAMA7_SFR_WPMR_KEY 0x53465200 /* SFR in ASCII*/ +#define SAMA7_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + +#define SAMA7_SFR_WPSR_WPSRC_MASK GENMASK(23, 8) +#define SAMA7_SFR_WPSR_WPVS_MASK BIT(0) + +#define SAMA7_SFR_CAN_SRAM_UPPER(x) BIT(x) + +#define SAMA7_SFR_UTMI_RX_VBUS BIT(25) /* VBUS Valid bit */ +#define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X BIT(23) /* TXPREEMPAMPTUNE 1x */ +#define SAMA7_SFR_UTMI_COMMONON BIT(3) /* PLL Common ON bit */ + +#define SAMA7_SFR_EHCIOHCI_PHYCLK BIT(1) /* Alternate PHY Clk */ + +#endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */