From patchwork Sun Nov 13 14:57:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1703242 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=j6IV5Pvd; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N9FtN4y90z23n0 for ; Mon, 14 Nov 2022 01:58:04 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 05CC385183; Sun, 13 Nov 2022 15:57:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="j6IV5Pvd"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4530D85169; Sun, 13 Nov 2022 15:57:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 32F3085176 for ; Sun, 13 Nov 2022 15:57:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668351437; x=1699887437; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c6Huu6YNM+iV4mhG40QDujODlQYlG4oZueNBqxManCA=; b=j6IV5Pvd0r6mr5rsNYpa12tO/mYBzmfYGYPPVLmLK5w1KIuCSRDOfzqT /6QSNG46sYpVnTa8+j2Y2Prl+DmKtVZ371PPlQwIT3rLWCbBKBVJnrk1s Dl3lqvdic+tJQsQLlEKWPx9tWKfZsNs6zbfAOXuTt8wTWvbU23YOMZ0pD ZNAFLtCN01b4Zgne3qHZivMshrsqoz8v723i04T8VVoUqGApHbQCWpuIr ZiSThCsle6gy0BjUjmBBYddSh1Sv0sIdXQZ+kCbVzoQ6LZbSA79gEKCDB dz7RvP0y/2Txer3NRarw8O1iZw9KzayFrdD0+9QWtcZcYJRKU4rsFFIMC g==; X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="292215256" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="292215256" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 06:57:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="967287427" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="967287427" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga005.fm.intel.com with ESMTP; 13 Nov 2022 06:57:10 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 2201E355A; Sun, 13 Nov 2022 22:57:10 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 219A0E0094D; Sun, 13 Nov 2022 22:57:10 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 4/5] arm: socfpga: soc64: Add f2s bridge support Date: Sun, 13 Nov 2022 22:57:05 +0800 Message-Id: <20221113145706.5002-4-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221113145706.5002-1-jit.loon.lim@intel.com> References: <20221113145706.5002-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #1508586908-5: Add F2H and F2SDRAM bridges disable/enable support, based on software programming flow in HW documentation. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/reset_manager_s10.c | 122 +++++++++++++++++++++- 1 file changed, 121 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 20ab374881..690cfb2b20 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -17,6 +17,57 @@ DECLARE_GLOBAL_DATA_PTR; +/* F2S manager registers */ +#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14 +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 + +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#define FLAGINSTATUS0_MPFE_NOC_IDLE (BIT(0) | BIT(4) | BIT(8)) +#define FLAGINSTATUS0_MPFE_NOC_IDLEACK (BIT(1) | BIT(5) | BIT(9)) +#define FLAGINSTATUS0_F2S_CMD_EMPTY (BIT(2) | BIT(6) | BIT(10)) +#define FLAGINSTATUS0_F2S_RESP_EMPTY (BIT(3) | BIT(7) | BIT(11)) + +#define FLGAOUTSET0_MPFE_NOC_IDLEREQ (BIT(0) | BIT(3) | BIT(6)) +#define FLGAOUTSET0_F2S_EN (BIT(1) | BIT(4) | BIT(7)) +#define FLGAOUTSET0_F2S_FORCE_DRAIN (BIT(2) | BIT(5) | BIT(8)) + +#define FLGAOUTCLR0_F2S_IDLEREQ (BIT(0) | BIT(3) | BIT(6)) +#else +#define FLAGINSTATUS0_MPFE_NOC_IDLE BIT(0) +#define FLAGINSTATUS0_MPFE_NOC_IDLEACK BIT(1) +#define FLAGINSTATUS0_F2S_CMD_EMPTY BIT(2) +#define FLAGINSTATUS0_F2S_RESP_EMPTY BIT(3) + +#define FLGAOUTSET0_MPFE_NOC_IDLEREQ BIT(0) +#define FLGAOUTSET0_F2S_EN BIT(1) +#define FLGAOUTSET0_F2S_FORCE_DRAIN BIT(2) + +#define FLGAOUTCLR0_F2S_IDLEREQ BIT(0) +#endif + +#define POLL_FOR_ZERO(expr, timeout_ms) \ + { \ + int timeout = (timeout_ms); \ + while ((expr)) { \ + if (!timeout) \ + break; \ + timeout--; \ + __socfpga_udelay(1000); \ + } \ + } + +#define POLL_FOR_SET(expr, timeout_ms) \ + { \ + int timeout = (timeout_ms); \ + while (!(expr)) { \ + if (!timeout) \ + break; \ + timeout--; \ + __socfpga_udelay(1000); \ + } \ + } + /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -57,6 +108,74 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } +static __always_inline void socfpga_f2s_bridges_reset(int enable) +{ + int timeout_ms = 300; + u32 empty; + + if (enable) { + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + BRGMODRST_FPGA2SOC_BRIDGES); + clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, + FLGAOUTSET0_MPFE_NOC_IDLEREQ); + + POLL_FOR_ZERO((readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & + FLAGINSTATUS0_MPFE_NOC_IDLEACK), timeout_ms); + clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, + FLGAOUTSET0_F2S_FORCE_DRAIN); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN); + + __socfpga_udelay(1); /* wait 1us */ + } else { + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN, + RSTMGR_HDSKEN_FPGAHSEN); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_HDSKACK), timeout_ms); + clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN); + __socfpga_udelay(1); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, + FLGAOUTSET0_F2S_FORCE_DRAIN); + __socfpga_udelay(1); + + do { + /* + * Read response queue status twice to ensure it is + * empty. + */ + empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & + FLAGINSTATUS0_F2S_RESP_EMPTY; + if (empty) { + empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & + FLAGINSTATUS0_F2S_RESP_EMPTY; + if (empty) + break; + } + + timeout_ms--; + __socfpga_udelay(1000); + } while (timeout_ms); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + BRGMODRST_FPGA2SOC_BRIDGES & + ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + FLGAOUTCLR0_F2S_IDLEREQ); + } +} + static __always_inline void socfpga_s2f_bridges_reset(int enable) { if (enable) { @@ -109,13 +228,14 @@ void socfpga_bridges_reset(int enable) hang(); } else { socfpga_s2f_bridges_reset(enable); - + socfpga_f2s_bridges_reset(enable); } } void __secure socfpga_bridges_reset_psci(int enable) { socfpga_s2f_bridges_reset(enable); + socfpga_f2s_bridges_reset(enable); } /*