From patchwork Sun Nov 13 14:57:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1703240 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=OeYCHq2G; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N9Fsz33YDz23mv for ; Mon, 14 Nov 2022 01:57:43 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0B4F485170; Sun, 13 Nov 2022 15:57:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OeYCHq2G"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BB57685169; Sun, 13 Nov 2022 15:57:21 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6321385170 for ; Sun, 13 Nov 2022 15:57:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668351436; x=1699887436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kaD+zPEKuXdBQLNzqIvYqXrqpigXfWTKtQabB/+KGlE=; b=OeYCHq2GXNotCyEWWUphyFQnuO/BHiulWIJ0G4bC2F2ckD0RefnCLeHy 6w8as4mZzOqcQIGz4Bu0gGBPhMYJx6Cp1YOPfc4okPjQWob0XIUM29tRr a7Mnc8HMptSaozKm9I+Rz2mEIz2QAVG6hdtjWbRWqzt7dRj88Ju19Vqr5 uSuRINBRzvsvs2uBOXf6tUKj1MA6vQwx5F5ylsqwS8RQ7K5sy1Nq9beCb ae0cuZHVxJm42Iu9pZn/7ni6oOKUfOmfMwO8vw0HhdxRJvCbwUHfM4dxB 5iyVYOwpiOo6a0bes423ZbDSzCJGccefzchMM6Qoiy3gOBO8wW+AuPTST A==; X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="292215255" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="292215255" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 06:57:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="967287425" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="967287425" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga005.fm.intel.com with ESMTP; 13 Nov 2022 06:57:10 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 814E43559; Sun, 13 Nov 2022 22:57:09 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 80A5BE0094D; Sun, 13 Nov 2022 22:57:09 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 3/5] arm: socfpga: soc64: Move bridges reset to common function Date: Sun, 13 Nov 2022 22:57:04 +0800 Message-Id: <20221113145706.5002-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221113145706.5002-1-jit.loon.lim@intel.com> References: <20221113145706.5002-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #1508586908-3: Move bridges reset code to common function, socfpga_s2f_bridges_reset(). This function is an inline function and can be included in normal U-boot and psci secure section. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/reset_manager_s10.c | 71 +++++++++++------------ 1 file changed, 35 insertions(+), 36 deletions(-) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f47fec10a0..20ab374881 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -57,32 +57,20 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } -void socfpga_bridges_reset(int enable) +static __always_inline void socfpga_s2f_bridges_reset(int enable) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) - u64 arg = enable; - - int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); - if (ret) { - printf("SMC call failed with error %d in %s.\n", ret, __func__); - return; - } -#else - u32 reg; - if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); - /* Release all bridges from reset state */ + /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~0); + BRGMODRST_SOC2FPGA_BRIDGES); /* Poll until all idleack to 0 */ - read_poll_timeout(readl, reg, !reg, 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); + POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), 300); } else { /* set idle request to all bridges */ writel(~0, @@ -93,30 +81,41 @@ void socfpga_bridges_reset(int enable) writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); - - /* Poll until all idlestatus to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS); - - /* Reset all bridges (except NOR DDR scheduler & F2S) */ + POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK) ^ + (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK), + 300); + + POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLESTATUS) ^ + (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK), + 300); + + /* Reset all SOC2FPGA bridges (except NOR DDR scheduler & F2S) */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + BRGMODRST_SOC2FPGA_BRIDGES); /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } -#endif +} + +void socfpga_bridges_reset(int enable) +{ + if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + u64 arg = enable; + + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0)) + hang(); + } else { + socfpga_s2f_bridges_reset(enable); + + } +} + +void __secure socfpga_bridges_reset_psci(int enable) +{ + socfpga_s2f_bridges_reset(enable); } /*