From patchwork Fri Nov 11 07:30:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dylan Hung X-Patchwork-Id: 1702441 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N7r3x23Vgz23mY for ; Fri, 11 Nov 2022 18:31:25 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 93BF6850FF; Fri, 11 Nov 2022 08:30:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E5950850D8; Fri, 11 Nov 2022 08:30:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3BD17850D6 for ; Fri, 11 Nov 2022 08:30:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dylan_hung@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 2AB76Zmj081439; Fri, 11 Nov 2022 15:06:35 +0800 (GMT-8) (envelope-from dylan_hung@aspeedtech.com) Received: from DylanHung-PC.aspeed.com (192.168.2.216) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Nov 2022 15:30:17 +0800 From: Dylan Hung To: , , , , CC: Subject: [PATCH 3/3] ram: ast2600: Align the RL and WL setting Date: Fri, 11 Nov 2022 15:30:08 +0800 Message-ID: <20221111073008.16364-4-dylan_hung@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111073008.16364-1-dylan_hung@aspeedtech.com> References: <20221111073008.16364-1-dylan_hung@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.216] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 2AB76Zmj081439 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Signed-off-by: Dylan Hung --- arch/arm/include/asm/arch-aspeed/sdram_ast2600.h | 4 ++++ drivers/ram/aspeed/sdram_ast2600.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h index d2408c0020f8..b0a91ae40d44 100644 --- a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h @@ -104,6 +104,10 @@ #define SDRAM_FORCE_PRECHARGE_EN BIT(4) #define SDRAM_REFRESH_EN BIT(0) +/* MCR14 */ +#define SDRAM_WL_SETTING GENMASK(23, 20) +#define SDRAM_CL_SETTING GENMASK(19, 16) + #define SDRAM_TEST_LEN_SHIFT 4 #define SDRAM_TEST_LEN_MASK 0xfffff #define SDRAM_TEST_START_ADDR_SHIFT 24 diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index bda02d062900..5d426088be3e 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea @@ -935,6 +936,7 @@ static void ast2600_sdrammc_lock(struct dram_info *info) static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) { int i; + u32 reg; writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); @@ -969,6 +971,13 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) writel(ddr4_ac_timing[i], ®s->ac_timing[i]); + /* update CL and WL */ + reg = readl(®s->ac_timing[1]); + reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING); + reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) | + FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5); + writel(reg, ®s->ac_timing[1]); + writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); writel(DDR4_MR45_MODE, ®s->mr45_mode_setting);