diff mbox series

[3/3] ram: ast2600: Align the RL and WL setting

Message ID 20221111073008.16364-4-dylan_hung@aspeedtech.com
State Accepted
Delegated to: Tom Rini
Headers show
Series Improve AST26x0 DDR4 timing and signal quality | expand

Commit Message

Dylan Hung Nov. 11, 2022, 7:30 a.m. UTC 
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
---
 arch/arm/include/asm/arch-aspeed/sdram_ast2600.h | 4 ++++
 drivers/ram/aspeed/sdram_ast2600.c               | 9 +++++++++
 2 files changed, 13 insertions(+)

Comments

Ryan Chen Nov. 24, 2022, 1:23 a.m. UTC | #1 
> -----Original Message-----
> From: Dylan Hung <dylan_hung@aspeedtech.com>
> Sent: Friday, November 11, 2022 3:30 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; ChiaWei Wang
> <chiawei_wang@aspeedtech.com>; joel@jms.id.au; Dylan Hung
> <dylan_hung@aspeedtech.com>; u-boot@lists.denx.de
> Cc: BMC-SW <BMC-SW@aspeedtech.com>
> Subject: [PATCH 3/3] ram: ast2600: Align the RL and WL setting
> 
> Use macro to represent the RL and WL setting to ensure the PHY and controller
> setting are aligned.
> 
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>

Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  arch/arm/include/asm/arch-aspeed/sdram_ast2600.h | 4 ++++
>  drivers/ram/aspeed/sdram_ast2600.c               | 9 +++++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> index d2408c0020f8..b0a91ae40d44 100644
> --- a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> @@ -104,6 +104,10 @@
>  #define SDRAM_FORCE_PRECHARGE_EN	BIT(4)
>  #define SDRAM_REFRESH_EN		BIT(0)
> 
> +/* MCR14 */
> +#define SDRAM_WL_SETTING		GENMASK(23, 20)
> +#define SDRAM_CL_SETTING		GENMASK(19, 16)
> +
>  #define SDRAM_TEST_LEN_SHIFT		4
>  #define SDRAM_TEST_LEN_MASK		0xfffff
>  #define SDRAM_TEST_START_ADDR_SHIFT	24
> diff --git a/drivers/ram/aspeed/sdram_ast2600.c
> b/drivers/ram/aspeed/sdram_ast2600.c
> index bda02d062900..5d426088be3e 100644
> --- a/drivers/ram/aspeed/sdram_ast2600.c
> +++ b/drivers/ram/aspeed/sdram_ast2600.c
> @@ -15,6 +15,7 @@
>  #include <asm/global_data.h>
>  #include <linux/err.h>
>  #include <linux/kernel.h>
> +#include <linux/bitfield.h>
>  #include <dt-bindings/clock/ast2600-clock.h>
> 
>  #define DDR_PHY_TBL_CHG_ADDR            0xaeeddeea
> @@ -935,6 +936,7 @@ static void ast2600_sdrammc_lock(struct dram_info
> *info)  static void ast2600_sdrammc_common_init(struct
> ast2600_sdrammc_regs *regs)  {
>  	int i;
> +	u32 reg;
> 
>  	writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
>  	writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key); @@
> -969,6 +971,13 @@ static void ast2600_sdrammc_common_init(struct
> ast2600_sdrammc_regs *regs)
>  	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
>  		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
> 
> +	/* update CL and WL */
> +	reg = readl(&regs->ac_timing[1]);
> +	reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
> +	reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
> +	       FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
> +	writel(reg, &regs->ac_timing[1]);
> +
>  	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
>  	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
>  	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
> --
> 2.25.1
Tom Rini Nov. 24, 2022, 9:33 p.m. UTC | #2 
On Fri, Nov 11, 2022 at 03:30:08PM +0800, Dylan Hung wrote:

> Use macro to represent the RL and WL setting to ensure the PHY and
> controller setting are aligned.
> 
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
index d2408c0020f8..b0a91ae40d44 100644
--- a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
+++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
@@ -104,6 +104,10 @@ 
 #define SDRAM_FORCE_PRECHARGE_EN	BIT(4)
 #define SDRAM_REFRESH_EN		BIT(0)
 
+/* MCR14 */
+#define SDRAM_WL_SETTING		GENMASK(23, 20)
+#define SDRAM_CL_SETTING		GENMASK(19, 16)
+
 #define SDRAM_TEST_LEN_SHIFT		4
 #define SDRAM_TEST_LEN_MASK		0xfffff
 #define SDRAM_TEST_START_ADDR_SHIFT	24
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index bda02d062900..5d426088be3e 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -15,6 +15,7 @@ 
 #include <asm/global_data.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
+#include <linux/bitfield.h>
 #include <dt-bindings/clock/ast2600-clock.h>
 
 #define DDR_PHY_TBL_CHG_ADDR            0xaeeddeea
@@ -935,6 +936,7 @@  static void ast2600_sdrammc_lock(struct dram_info *info)
 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
 {
 	int i;
+	u32 reg;
 
 	writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
 	writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
@@ -969,6 +971,13 @@  static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
 
+	/* update CL and WL */
+	reg = readl(&regs->ac_timing[1]);
+	reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
+	reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
+	       FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
+	writel(reg, &regs->ac_timing[1]);
+
 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);