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07 Nov 2022 05:34:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="725138775" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="725138775" Received: from pglmail07.png.intel.com ([10.221.193.207]) by FMSMGA003.fm.intel.com with ESMTP; 07 Nov 2022 05:34:20 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 35B7F4838; Mon, 7 Nov 2022 21:34:20 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 34A6CE00214; Mon, 7 Nov 2022 21:34:20 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , "Chew, Chiau Ee" , Chew@ecsmtp.png.intel.com Subject: [PATCH 2/3] Set/clear reset_req bit before/after PR Date: Mon, 7 Nov 2022 21:33:50 +0800 Message-Id: <20221107133351.26311-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221107133351.26311-1-jit.loon.lim@intel.com> References: <20221107133351.26311-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: "Chew, Chiau Ee" HSD #1508949110: For Agilex and Stratix10, before FPGA Partial Reconfiguration (PR) operation, SW need to set reset_req bit in freeze_csr_ctrl register to reset PR region. The same bit need to be cleared after FPGA PR operation is done. Signed-off-by: Chew, Chiau Ee Signed-off-by: Jit Loon Lim --- drivers/fpga/intel_pr.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/intel_pr.c b/drivers/fpga/intel_pr.c index 6637425452..a0a758488b 100644 --- a/drivers/fpga/intel_pr.c +++ b/drivers/fpga/intel_pr.c @@ -81,10 +81,17 @@ static int intel_freeze_br_do_freeze(unsigned int region) writel(FREEZE_CSR_CTRL_FREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); - return wait_for_bit_le32((const u32 *)(addr + + ret = wait_for_bit_le32((const u32 *)(addr + FREEZE_CSR_STATUS_OFFSET), FREEZE_CSR_STATUS_FREEZE_REQ_DONE, true, FREEZE_TIMEOUT, false); + + if (ret) + writel(0, addr + FREEZE_CSR_CTRL_OFFSET); + else + writel(FREEZE_CSR_CTRL_RESET_REQ, addr + FREEZE_CSR_CTRL_OFFSET); + + return ret; } static int intel_freeze_br_do_unfreeze(unsigned int region) @@ -97,6 +104,8 @@ static int intel_freeze_br_do_unfreeze(unsigned int region) if (ret) return ret; + writel(0, addr + FREEZE_CSR_CTRL_OFFSET); + status = readl(addr + FREEZE_CSR_STATUS_OFFSET); if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) @@ -106,10 +115,14 @@ static int intel_freeze_br_do_unfreeze(unsigned int region) writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); - return wait_for_bit_le32((const u32 *)(addr + + ret = wait_for_bit_le32((const u32 *)(addr + FREEZE_CSR_STATUS_OFFSET), FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE, true, FREEZE_TIMEOUT, false); + + writel(0, addr + FREEZE_CSR_CTRL_OFFSET); + + return ret; } static int do_pr(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])