| Message ID | 20221014094935.653862-6-pan@semihalf.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Update Chameleon v3 configuration | expand |
On Fri, 14 Oct 2022 at 03:49, Paweł Anikiel <pan@semihalf.com> wrote: > > Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the > Mercury+ AA1 module > > Signed-off-by: Paweł Anikiel <pan@semihalf.com> > --- > arch/arm/dts/Makefile | 1 + > .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi | 12 ++++++++++++ > arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts | 5 +++++ > 3 files changed, 18 insertions(+) > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts > Reviewed-by: Simon Glass <sjg@chromium.org>
On Fri, Oct 14, 2022 at 2:49 AM Paweł Anikiel <pan@semihalf.com> wrote: > > Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the > Mercury+ AA1 module > > Signed-off-by: Paweł Anikiel <pan@semihalf.com> > --- > arch/arm/dts/Makefile | 1 + > .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi | 12 ++++++++++++ > arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts | 5 +++++ > 3 files changed, 18 insertions(+) > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 9b00b64509..fc6f6be567 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -429,6 +429,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ > socfpga_agilex_socdk.dtb \ > socfpga_arria5_secu1.dtb \ > socfpga_arria5_socdk.dtb \ > + socfpga_arria10_chameleonv3_270_2.dtb \ > socfpga_arria10_chameleonv3_270_3.dtb \ > socfpga_arria10_chameleonv3_480_2.dtb \ > socfpga_arria10_socdk_sdmmc.dtb \ > diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi > new file mode 100644 > index 0000000000..05b4485cf3 > --- /dev/null > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi > @@ -0,0 +1,12 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2022 Google LLC > + */ > +#include "socfpga_arria10_chameleonv3_480_2_handoff.h" > +#include "socfpga_arria10-handoff.dtsi" > +#include "socfpga_arria10_handoff_u-boot.dtsi" > +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi" > + > +&fpga_mgr { > + altr,bitstream = "fpga-270-2.itb"; > +}; > diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts > new file mode 100644 > index 0000000000..bef0280212 > --- /dev/null > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts > @@ -0,0 +1,5 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2022 Google LLC > + */ > +#include "socfpga_arria10_chameleonv3.dtsi" > -- > 2.38.0.413.g74048e4d9e-goog > Reviewed-by: Alexandru Stan <amstan@chromium.org> Tested-by: Alexandru Stan <amstan@chromium.org>
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9b00b64509..fc6f6be567 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -429,6 +429,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3_270_2.dtb \ socfpga_arria10_chameleonv3_270_3.dtb \ socfpga_arria10_chameleonv3_480_2.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi new file mode 100644 index 0000000000..05b4485cf3 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3_480_2_handoff.h" +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi" + +&fpga_mgr { + altr,bitstream = "fpga-270-2.itb"; +}; diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts new file mode 100644 index 0000000000..bef0280212 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3.dtsi"
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the Mercury+ AA1 module Signed-off-by: Paweł Anikiel <pan@semihalf.com> --- arch/arm/dts/Makefile | 1 + .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts | 5 +++++ 3 files changed, 18 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts