| Message ID | 20221014070018.30280-1-peterlin@andestech.com |
|---|---|
| State | Accepted |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: andes_plic.c: use modified IPI scheme | expand |
> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com> > Sent: Friday, October 14, 2022 3:00 PM > To: u-boot@lists.denx.de > Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com> > Subject: [PATCH] riscv: andes_plic.c: use modified IPI scheme > > The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > arch/riscv/lib/andes_plic.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 5e113ee8c9..9fe2568a16 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -27,17 +27,18 @@ /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) -#define ENABLE_HART_IPI (0x80808080) -#define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) +#define ENABLE_HART_IPI (0x01010101) +#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) DECLARE_GLOBAL_DATA_PTR; -static int enable_ipi(int hart) +int enable_ipi(int hart) { unsigned int en; - en = ENABLE_HART_IPI >> hart; + en = ENABLE_HART_IPI << hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); return 0; }
The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- arch/riscv/lib/andes_plic.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)