From patchwork Mon Sep 5 12:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1674261 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=LuQt/uKT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MLpQm3cPqz1yhk for ; Mon, 5 Sep 2022 22:55:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A9ECC848C4; Mon, 5 Sep 2022 14:55:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LuQt/uKT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E4DA084913; Mon, 5 Sep 2022 14:55:21 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 57CCD8486B for ; Mon, 5 Sep 2022 14:55:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662382519; x=1693918519; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=nuCB0AzqpA6S1hLnNZlN5Sx9xVPSkMIQ4EAuhfSp1Jg=; b=LuQt/uKThgcsVuFEBZTLCFl079gM21mjW5aQtqVW+Fn7umyu3YMaJh9C d7ElFEqzbFgrbvgNpvUUpgReOfaI/UxFDWIJRN0Pi6xQF+u2xk6HDXnav 8gqkYIlwdNE34oFdUP0CZ/hF0wWhMRFbcIt0sFs0XI+tnWP8UclCck6db yofUyZY1YrNjfeUA26tGWgx2WYIDEby2c8kqnCW50Ef8kFZu07+JZW2UK +zCTdUhQjPmzCXe/ZeXN3DNWEBmZNLURAFkKsu0hO3ve2qBauAP0f3B0b vubRZIFxhgwKB9DFdL6p6fYi7P6Zmxic8mP6ttcJpIbVfzNUveNqjNzXK A==; X-IronPort-AV: E=McAfee;i="6500,9779,10460"; a="358099222" X-IronPort-AV: E=Sophos;i="5.93,291,1654585200"; d="scan'208";a="358099222" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2022 05:55:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,291,1654585200"; d="scan'208";a="739586084" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga004.jf.intel.com with ESMTP; 05 Sep 2022 05:55:13 -0700 Received: from localhost (pgli0117.png.intel.com [10.221.240.80]) by pglmail07.png.intel.com (Postfix) with ESMTP id DA0C832EB; Mon, 5 Sep 2022 20:55:12 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id D49CF3D21; Mon, 5 Sep 2022 20:55:12 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Sieu Mun Tang , Jit Loon Lim Subject: [PATCH] arm: Enable cache-pl310 driver build for both SPL and proper U-Boot Date: Mon, 5 Sep 2022 20:55:11 +0800 Message-Id: <20220905125511.14495-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Moved CONFIG_SYS_L2_PL310 to the location where the build on the cache-pl310 can be taken in both SPL and proper U-Boot. This driver is required for SoCFPGA when temporarily turning on the cache for better performance in initializing whole DDR to zero. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- arch/arm/lib/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..575042e6df 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -43,6 +43,7 @@ ifdef CONFIG_ARM64 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o else +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif